Fetch Stage Indirect Jump Handling in Processor Pipelines
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Solution Overview
Problem
In processor pipelines, indirect jump target predictors often generate mispredictions, leading to performance penalties and power wastage, especially when handling sequences of instructions that form immediate jumps, as they continue to predict target addresses unnecessarily.
Innovation Solution
The implementation of circuitry to detect sequences of instructions forming immediate jumps in the fetch stage of the processor pipeline, allowing for the determination of target addresses and disabling the indirect jump target predictor to prevent unnecessary predictions, thereby reducing power consumption and pollution of the predictor state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the indirect jump target predictor circuit generates target address predictions for all indirect jump instructions, then the processor can fetch upcoming instructions in advance, but mispredictions occur causing performance penalties and power wastage
Solution Approach 1:
The patent applies preliminary action by detecting sequences of instructions that form immediate jumps before they reach the indirect jump target predictor circuit. The detection circuitry identifies patterns such as AUIPC followed by JALR instructions and determines their target addresses in advance, allowing the predictor circuit to be disabled for these sequences and avoid unnecessary power consumption while maintaining accurate instruction fetching
2Ease of operation
If the indirect jump target predictor circuit continues to predict target addresses for sequences forming immediate jumps, then the circuit remains active and simple to operate, but it generates mispredictions and pollutes the predictor state
Solution Approach 1:
The patent extracts sequences of instructions that form immediate jumps from the general indirect jump instruction stream. By identifying these specific sequences through detection circuitry and handling them separately with direct target address calculation, the indirect jump target predictor circuit is prevented from processing these sequences, thereby eliminating mispredictions and state pollution while maintaining accurate prediction for other indirect jumps
3Adaptability or versatility
If the processor uses data-dependent indirect jump instructions, then flexible control flow is achieved, but the target address is not available until later pipeline stages causing performance loss
Solution Approach 1:
The patent applies preliminary action by detecting sequences where the target address can be computed in advance using program counter values and immediate fields. For detected immediate jump sequences, the target address is determined in the fetch stage before the data-dependent indirect jump instruction reaches later pipeline stages, eliminating pipeline stalls while maintaining control flow flexibility
Data Source
AI summary
Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.