Instruction Fetch Unit Offset Adder for Branch Handling
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Solution Overview
Problem
In processors with a single program counter, determining the address of an instruction currently being executed and the address of an instruction to be fetched after a change in program flow is inefficient, requiring costly software calculations and resource-intensive methods.
Innovation Solution
A device with a register for storing an instruction address and an adder that adds a predetermined amount to this address to determine the position in the program flow, resetting and incrementing this amount in response to changes in program flow to fetch consecutive instructions efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software is used to calculate instruction addresses after program flow changes, then flexibility and adaptability are improved, but processing time and computational resources increase significantly
Solution Approach 1:
The patent replaces software-based calculation with a hardware adder circuit that automatically computes instruction addresses by adding a predetermined amount to the program counter value, eliminating the need for software intervention and reducing processing time
Solution Approach 2:
The adder circuit automatically updates instruction addresses following program flow changes without requiring external software control, making the system self-sufficient in handling address calculation after interrupts or branch operations
2Device complexity
If a single program counter is used to reduce gate count, then device complexity is reduced, but the ability to track multiple instruction addresses simultaneously deteriorates
Solution Approach 1:
The patent resolves the single program counter limitation by introducing a temporal dimension through a predetermined amount offset, allowing the system to derive addresses for instructions at different pipeline stages from a single program counter value without requiring multiple physical counters
3Measurement precision
If conventional software methods are used to determine current instruction address, then accuracy is improved, but power consumption and area usage increase
Solution Approach 1:
The patent replaces power-intensive software calculation with a low-power hardware adder circuit that performs address derivation through simple arithmetic operations, significantly reducing power consumption while maintaining address determination accuracy
Data Source
AI summary
This application is concerned with a device and method for fetching instructions from a data store for processing by a data processor. The device comprises: a register for storing an address of an instruction to be processed by said data processor; a fetch unit responsive to an address input to said fetch unit to fetch an instruction stored at said address; an adder for adding a predetermined amount to said address stored in said register prior to sending said address to said fetch unit, said predetermined amount determining a position in a program flow said fetched instruction has with respect to said instruction addressed in said register; said adder being responsive to detection of a change in program flow to reset said predetermined amount to an initial value, and to increase said predetermined amount for subsequent fetches by an amount equal to the separation between addresses such that consecutive addresses are fetched up to a maximum predetermined amount.