FeTFT Source-Drain Layering for Defect and Resistance Control
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Solution Overview
Problem
The formation of defects in source/drain structures during the deposition of Ferroelectric Thin-Film Transistor (FeTFT) memory cells leads to increased resistance and reduced device performance, affecting the uniformity and reliability of memory cells in semiconductor memories.
Innovation Solution
A two-layer source/drain structure is implemented, where a first source/drain layer is deposited and then etched to reduce defect size, followed by a second source/drain layer deposition, which covers any defects in the first layer, providing a less resistive interface and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single source/drain layer is deposited, then the manufacturing process is simple, but defects form due to topography leading to increased resistance and reduced device uniformity
Solution Approach 1:
The source/drain structure is divided into multiple layers (first source/drain layer and second source/drain layer) to address defect formation issues. Each layer serves a specific function: the first layer provides initial coverage while the second layer compensates for defects and reduces resistance, thereby improving device uniformity without excessive complexity increase.
Solution Approach 2:
The patent employs a composite multi-layer source/drain structure where different materials or processed versions of the same material are stacked. This composite approach allows each layer to contribute different properties (e.g., defect coverage, conductivity) that collectively improve device uniformity and performance.
2Reliability
If a two-layer source/drain structure is employed, then defects are reduced and device performance is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The first source/drain layer is deposited and processed (including selective removal in recesses) before the second layer is added. This preliminary action prepares the structure by creating controlled recesses and removing defective portions, allowing the second layer to be deposited in a optimized configuration that enhances reliability.
Solution Approach 2:
The patent applies different treatments to different regions of the source/drain structure. Specifically, the first source/drain layer is selectively removed in recesses while being retained in other areas, and the second layer is deposited to specific thicknesses in different regions. This local differentiation optimizes device performance while managing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by reducing resistance, improving uniformity, and increasing current within memory cells, thereby enhancing the reliability and consistency of FeTFT memory cells.
Implementation Method 1
depositing a memory layer on the first conductive feature... forming a ferroelectric layer over the word line
Implementation Method 2
depositing a first source/drain layer in the first opening and the second opening... depositing a second source/drain layer on the first source/drain layer
Data Source
AI summary
A device includes a memory layer over a substrate; a first source/drain structure and a second source/drain structure on the memory layer, wherein the first source/drain structure and the second source drain structure each include a first source/drain layer on the memory layer; a second source/drain layer on the first source/drain layer, wherein the second source/drain layer is different from the first source/drain layer; and a metal layer on the second source/drain layer; and a channel region extending on the memory layer from the first source/drain layer of the first source/drain structure to the first source/drain layer of the second source/drain structure.