Ferroelectric Gate Oxide Tunnel FeFET Memory
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Solution Overview
Problem
Ferroelectric transistors face challenges with poor memory window and low Ron/Roff ratio, limiting their scalability and variability in non-volatile memory applications, despite previous efforts to improve these aspects through gate stack engineering and process optimizations.
Innovation Solution
A tunnel FET configuration utilizing ferroelectric gate oxide to modulate the channel's conductivity, enabling wider memory windows and higher Ron/Roff ratios through controlled polarization charge and dopant profiles, resulting in steep subthreshold Id-Vg slopes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate stack engineering and process optimizations are used to improve memory window and Ron/Roff ratio, then memory performance is improved, but intrinsic variability still limits operating windows in large sized arrays
Solution Approach 1:
The patent applies local quality by creating an asymmetric dopant profile in the channel region with different doping concentrations at different locations. Specifically, the channel has a first dopant concentration near the source and a second dopant concentration near the drain, with the ratio between them being optimized. This local variation in dopant concentration allows different regions of the channel to have optimized properties for their specific function, improving overall device performance and reducing variability
Solution Approach 2:
The patent employs parameter changes by systematically optimizing the dopant concentration ratio in the channel region. The dopant concentration ratio is adjusted within a specific range (0.1 to 10) to achieve the desired balance between memory window and Ron/Roff ratio. By changing this critical parameter, the device achieves improved performance characteristics that are robust against intrinsic variability in large arrays
2Device complexity
If conventional FeFET structures are used, then device simplicity is maintained, but memory window and Ron/Roff ratio remain poor
Solution Approach 1:
The patent introduces local quality by implementing an asymmetric dopant profile in the channel region. Instead of uniform doping, the channel has different dopant concentrations at different positions, with a optimized ratio between source-side and drain-side concentrations. This local differentiation enables the transistor to achieve superior memory window and Ron/Roff ratio while maintaining overall structural simplicity
Solution Approach 2:
The patent applies partial action by selectively doping only specific regions of the channel rather than the entire channel uniformly. The dopant is introduced with controlled concentrations in different channel segments, creating the asymmetric profile needed for improved performance without requiring complete restructuring of the device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high switching speed and improved scalability by enhancing memory windows and Ron/Roff ratios, overcoming intrinsic variability challenges and enabling continued scaling of memory arrays.
Implementation Method 1
A ferroelectric material on a bottom, a first side and a second side of the gate electrode, and above the intrinsic region
Implementation Method 2
A tunnel FET configuration utilizing ferroelectric gate oxide to modulate the channel's conductivity
Data Source
AI summary
A transistor is disclosed. The transistor includes a p-type region, an intrinsic region coupled to the p-type region, an n-type region coupled to the intrinsic region, and a gate electrode above the intrinsic region. The ferroelectric material is on a bottom, a first side and a second side of the gate electrode, and above the intrinsic region.