FinFET Leakage Reduction via Epitaxial Oxidation Isolation

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Solution Overview

Problem

The implementation of FinFETs faces challenges due to poor isolation between adjacent fins, leading to high leakage current and degraded device performance.

Innovation Solution

A simple and cost-effective process flow is developed to achieve an undoped channel in FinFETs by varying the oxidation of epitaxial semiconductor layers in different regions, allowing for tensile strain enhancement in n-type devices while avoiding strain penalties in p-type devices, and optimizing performance through epitaxial growth of semiconductor fins as blanket layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If FinFETs are implemented with vertical fins extending from substrate, then device density and performance are improved, but leakage current increases due to poor isolation between adjacent fins

Engineering Contradiction:
Improvedevice densityVSAvoidleakage current
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The substrate is divided into multiple isolated fin structures with deep trenches between them. Each fin is separated by isolation regions extending into the substrate, creating discrete semiconductor devices that prevent electrical interaction and leakage current between adjacent fins while maintaining high device density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Isolation regions filled with dielectric material are introduced as intermediary structures between adjacent fins. These isolation regions extend deep into the substrate and act as electrical barriers, preventing leakage current while allowing the fins to maintain their vertical structure for high density.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If epitaxial semiconductor layers are grown as blanket layers, then manufacturing complexity is reduced and cost is decreased, but precise control of strain in different device regions becomes challenging

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidstrain control precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

Different epitaxial layers are grown with different material compositions and strain characteristics in different regions of the substrate. N-type devices receive layers optimized for tensile strain while p-type devices receive layers optimized for compressive strain, achieving precise local strain control through region-specific epitaxial growth parameters.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The epitaxial growth process parameters such as temperature, pressure, gas flow rates, and material composition are varied to control the strain characteristics of different semiconductor layers. By adjusting these parameters during sequential layer growth, precise strain control is achieved in different device regions while maintaining a relatively simple blanket growth process.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances device performance by reducing leakage current and improving isolation, resulting in a more efficient and cost-effective FinFET design with a channel on insulator scheme.

Implementation Method 1

epitaxial growth of semiconductor fins as blanket layers

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

varying the oxidation of epitaxial semiconductor layers in different regions

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS10163903B2FETS and methods of forming FETS
Publication Date: 2018.12.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10163903B2 patent drawing
  • US10163903B2 patent drawing
  • US10163903B2 patent drawing

AI summary

A method includes forming a first semiconductor strip on a substrate, the first semiconductor strip including a first crystalline semiconductor material on a substrate and a second crystalline semiconductor material above the first crystalline semiconductor material. A first portion of the first crystalline semiconductor material in first semiconductor strip is converted to a dielectric material, where a second portion of the first crystalline semiconductor material remains unconverted. Gate structures are formed over the first semiconductor strip and source/drain regions are formed on opposing sides of the gate structures.