FFE CTLE with SF-CS Stage for 28GHz Low Power Equalization
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Solution Overview
Problem
Existing receiver equalization circuits for high-speed serial links and wireline transceivers face challenges in achieving low power consumption, high driving strength, low noise, and reduced input loading while operating effectively at high frequencies such as 28GHz, as current designs either perform poorly or consume excessive power due to the need for multiple stages.
Innovation Solution
A low power receiver employing a feedforward equalization-based continuous time linear equalizer (FFE CTLE) design that reuses a source-follower transistor as a common-source input device, incorporating a single SF-CS stage for both scaling and delay functions, and an LC delay line to provide peaking without excessive attenuation, thereby reducing power usage and input loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If RC-degenerated CTLE design is used for high frequency peaking, then high frequency gain is improved, but the shunt capacitor value becomes infeasibly small and the circuit is limited by inherent parasitics
Solution Approach 1:
The patent combines the source-follower transistor and common-source transistor into a single integrated SF-CS stage, merging multiple functions (scaling, delay, subtraction) into one unified circuit block. This integration eliminates the need for separate buffer stages and reduces the overall circuit complexity while maintaining high frequency performance.
Solution Approach 2:
The source-follower transistor is designed to serve multiple functions: it acts as both a scaling element and a buffer stage, while also providing input impedance transformation. This multi-functionality reduces the total number of components needed and simplifies the circuit architecture.
2Use of energy by moving object
If multiple summer and buffer stages are added to achieve low power operation, then power consumption is reduced, but device complexity and input loading increase
Solution Approach 1:
The patent merges the summer function and buffer function into a single SF-CS stage, eliminating the need for separate summer and buffer stages. This integration achieves low power operation while reducing device complexity and minimizing input loading effects.
Solution Approach 2:
The source-follower transistor automatically provides buffering and impedance transformation without requiring additional active control or separate stages. The circuit leverages the inherent properties of the SF-CS configuration to achieve power efficiency without increasing complexity.
3Reliability
If conventional CTLE designs are used at 28GHz, then equalization is achieved, but the circuit becomes extremely complex to implement
Solution Approach 1:
The patent segments the equalization function into distinct frequency bands: the source-follower path handles low-frequency signal scaling, while the common-source path with LC delay line handles high-frequency peaking. This segmentation allows each path to be optimized independently, simplifying the overall implementation at 28GHz.
Solution Approach 2:
The patent combines multiple equalization functions (scaling, delay, peaking, subtraction) into a single integrated SF-CS stage, dramatically reducing implementation complexity compared to conventional multi-stage designs while maintaining equalization performance at 28GHz.
Data Source
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AI summary
A low power receiver having a feedforward equalization, FFE, based continuous time linear equalizer, CTLE. The FFE CTLE comprises: an input for receiving an input signal (510); a main first path (532) operably coupled to the input and comprising a source-follower transistor (520) arranged to apply a scaling factor to the received input signal; a second path (560) operably coupled to the input and comprising a delay (540) arranged to apply a delay to the received input signal and a common source transistor (530) arranged to apply a scaling factor to the received delayed input signal, wherein the source-follower transistor and the common source, CS, transistor are connected as a single SF-CS stage whose output is arranged to subtract the output of the common source transistor from an output of the source-follower transistor.