Feed-Forward Equalizer Sampling for Low-Complexity Timing Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital telecommunications systems face challenges in optimizing clock recovery due to inter-symbol interference (ISI), with current filter structures not adequately balancing performance and complexity, particularly in fractional Feed-Forward Equalizers (FFEs) that require increased sampling rates and complexity.
Innovation Solution
The proposed solution involves an equalizer configuration that samples input signals at intervals more than one sample period away from the reference, with a delay value less than the sample period, to obtain strongly correlated future and past bits while minimizing correlation with bit transitions, thereby optimizing timing recovery with reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fractional FFEs are used to improve timing recovery performance, then filtering performance is improved, but device complexity increases due to more input samplers and reference clock generation
Solution Approach 1:
The patent divides the filtering function into two separate equalizers: a first equalizer for data recovery and a second equalizer for timing recovery. Each equalizer processes samples independently with optimized filter coefficients, avoiding the need for fractional sampling and multiple reference clocks while achieving comparable performance to fractional FFEs.
Solution Approach 2:
The patent enables a single integer-sampled FFE structure to serve dual purposes: data recovery and timing recovery. By optimizing filter coefficients for each function separately, the system achieves performance comparable to specialized fractional FFEs without requiring additional hardware complexity.
2Reliability
If the filter length is increased to improve performance, then filtering performance is improved, but device complexity increases
Solution Approach 1:
The patent applies different filter coefficient optimizations to different functional components: the first equalizer uses coefficients optimized for data recovery while the second equalizer uses coefficients optimized for timing recovery. This localized optimization allows each component to achieve maximum performance with minimal filter length, avoiding the need for uniformly long filters.
3Device complexity
If sampling is performed at integer multiples of unit interval to reduce complexity, then device complexity is reduced, but timing recovery performance deteriorates due to ISI
Solution Approach 1:
The patent uses timing error signals generated from the second equalizer (optimized for timing recovery) to adjust the sampling phase. This feedback mechanism allows the system to compensate for ISI effects and optimize timing recovery performance while maintaining simple integer-sampled architecture.
Data Source
AI summary
An equalizer is disclosed, and associated operational method. The equalizer has a configuration that balances performance and complexity by obtaining samples that are strongly correlated with future and past transmitted bits, and are weakly correlated with future and past bit transitions, and is useful for timing recovery circuits. Samples are only obtained or collected at time intervals more than one sample period away from the reference sample. Samples are shifted by a delay value less than the sample period, and are obtained at a sample period of one unit interval. A means to adjust the sampling point delay is also disclosed. In an implementation, samples that are within the sample period away from the reference sample are obtained and used for implementing a timing shift, not for equalization of the timing recovery signal. Embodiments are also disclosed for optimizing performance for data recovery.