FFS LCD Array Substrate Same-Plane Electrode Connection

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Solution Overview

Problem

Conventional fringe field switching (FFS) type liquid crystal display (LCD) panels have a low aperture ratio due to the need for through holes to electrically connect pixel electrodes to drain electrodes, which decreases the effective viewing angle and increases the cost of the backlight module.

Innovation Solution

The array substrate design allows pixel electrodes to directly contact drain electrodes without through holes, increasing the aperture ratio and eliminating the need to consider the distance between common electrodes and gate lines, thereby enhancing the viewing angle and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pixel electrodes are electrically connected to drain electrodes by through holes, then electrical connection is achieved, but aperture ratio decreases

Engineering Contradiction:
Improveelectrical connectionVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent removes the through-hole structure from the pixel electrode connection method. Instead of connecting pixel electrodes to drain electrodes through holes in the passivation layer, the pixel electrodes are extended to directly contact the drain electrodes on the same plane, eliminating the need for through holes and thereby increasing the aperture ratio.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a vertical connection approach (through holes penetrating the passivation layer) to a horizontal connection approach (pixel electrodes extending laterally to contact drain electrodes on the same plane). This dimensional change eliminates the need for through holes while maintaining electrical connectivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If distance between common electrode and gate line is increased, then electrical isolation is improved, but aperture ratio decreases

Engineering Contradiction:
Improveelectrical isolationVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the common electrode and gate line onto the same plane, eliminating the need for vertical stacking and associated spacing requirements. This integration allows for more efficient use of space and improves aperture ratio while maintaining proper electrical isolation through the insulating layer.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design increases the aperture ratio of the pixel, improving the viewing angle and reducing the cost of the backlight module, making it more competitive in the market for middle and small-sized LCD panels.

Implementation Method 1

The pixel electrodes and the common electrode can be acted as upper and lower electrodes respectively so as to form a transverse electric field. The transverse electric field can control the rotation of LC molecules in an LC layer between the upper and lower substrates.

Methodology Applied
Scientific EffectTransverse electric field: Electric Field

Implementation Method 2

The refractive indexes of major axis and minor axis of a liquid crystal (LC) molecule in the LCD panel are different, and thus an image depends on the viewing angle of a viewer when the viewer watches the screen of the LCD panel.

Methodology Applied
Scientific EffectBirefringence: Birefringence

Data Source

PatentUS8451413B2Array substrate for FFS type LCD panel and method for manufacturing the same
Publication Date: 2013.05.28 HANNSTAR DISPLAY CORP
  • US8451413B2 patent drawing
  • US8451413B2 patent drawing
  • US8451413B2 patent drawing

AI summary

An array substrate for FFS type LCD panel includes a transparent substrate, gate lines, a gate insulating layer, data lines, pixel electrodes, a passivation layer and a common electrode. The gate lines are disposed on the transparent substrate. The gate insulating layer is disposed on the transparent substrate and covers the gate lines. The data lines are disposed on the gate insulating layer. The pixel electrodes are disposed on the gate insulating layer, wherein the pixel electrodes and the data lines are located on the same level. The passivation layer is disposed on the gate insulating layer and covers the pixel electrodes and the data lines. The common electrode is disposed on the passivation layer.