FFS LCD Array Substrate Reducing Mask Processes and Signal Delays

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Solution Overview

Problem

The existing array substrates for fringe field switching (FFS) mode liquid crystal display (LCD) devices require multiple mask processes, leading to increased manufacturing time, costs, and signal delays due to longer signal lines, which affect productivity and image quality.

Innovation Solution

A method for manufacturing an array substrate with reduced mask processes, using a gate line and gate electrode, forming a pixel electrode, gate insulating layer, data line, source and drain electrodes, and a passivation layer, with a common electrode having bar-shaped openings, and a connection pattern that contacts the drain and pixel electrodes through specific contact holes, while utilizing copper or copper alloy for low resistivity signal lines to prevent signal delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple mask processes are used to manufacture the array substrate, then the manufacturing precision and structural complexity are improved, but the manufacturing time and costs increase

Engineering Contradiction:
Improvesubstrate structure precisionVSAvoidmanufacturing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent combines multiple mask processes into a single integrated manufacturing step. Specifically, the pixel electrode, common electrode, and connection patterns are formed simultaneously through one mask process rather than sequentially through multiple separate mask processes, thereby reducing manufacturing time while maintaining structural precision

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single mask process serves multiple functions: it defines the pixel electrode pattern, the common electrode pattern with bar-shaped openings, and the connection patterns all in one operation. This multi-functional approach eliminates the need for separate mask processes for each component

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If multiple mask processes are used to manufacture the array substrate, then the manufacturing precision is improved, but the manufacturing costs increase

Engineering Contradiction:
Improvesubstrate structure precisionVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

By merging multiple mask processes into one, the patent reduces the total number of manufacturing steps, which directly lowers manufacturing costs while preserving the precision required for the substrate structure through the integrated design of the single mask process

Inventive Principle:
Principle #5Merging (Combining)

3Area of stationary object

If longer signal lines are used in the array substrate, then the device area is increased, but signal delays occur affecting image quality

Engineering Contradiction:
Improvedevice areaVSAvoidsignal quality
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent changes the material parameter of the signal lines by using copper or copper alloy instead of conventional materials. This material substitution reduces resistivity and prevents signal delays, allowing the device to maintain larger area while preserving signal quality and image quality

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8803147B2Array substrate for fringe field switching mode liquid crystal display device and method of manufacturing the same
Publication Date: 2014.08.12 LG DISPLAY CO LTD
  • US8803147B2 patent drawing
  • US8803147B2 patent drawing
  • US8803147B2 patent drawing

AI summary

A method of manufacturing an array substrate for an FFS mode LCD device includes forming a gate line and a gate electrode on a substrate, forming a pixel electrode in the pixel region, forming a gate insulating layer on the gate line, the gate electrode and the pixel electrode, forming a data line, a source electrode, a drain electrode, and a semiconductor layer on the gate insulating layer, forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer including a drain contact hole and a pixel contact hole, and forming a connection pattern and a common electrode on the passivation layer, wherein the common electrode includes bar-shaped first openings in the pixel region, and the connection pattern contacts the drain electrode and the pixel electrode through the drain contact hole and the pixel contact hole, respectively.