FFS Mode LCD Manufacturing Reducing Dielectric Layers
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Solution Overview
Problem
The existing manufacturing methods for FFS mode LCDs result in unbalanced driving voltage due to thick dielectric layers, causing image sticking issues.
Innovation Solution
A method that reduces the number of dielectric layers between the common electrode and the pixel electrode by optimizing the layer formation process, including the use of a passivation layer as the sole dielectric layer and positioning the common line between the passivation layer and the common electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two dielectric layers (gate insulating layer and passivation layer) are used between common electrode and pixel electrode, then the manufacturing process provides adequate insulation and structural support, but the driving voltage becomes unbalanced between odd and even frames causing image sticking
Solution Approach 1:
The gate insulating layer is removed from between the common electrode and pixel electrode, extracting only the necessary dielectric layer (passivation layer) to maintain insulation while reducing the total number of dielectric layers from two to one, thereby resolving the voltage balance issue
Solution Approach 2:
The dielectric function is segmented and reassign ed: the passivation layer remains to provide insulation between common electrode and pixel electrode, while the gate insulating layer is eliminated in this specific region, allowing separate optimization of insulation requirements
2Reliability
If common line is positioned between gate insulating layer and common electrode, then the manufacturing process follows conventional layering, but the thick dielectric layers cause unbalanced driving voltage
Solution Approach 1:
The gate insulating layer is extracted from the path between common electrode and pixel electrode, reducing the total thickness of dielectric layers and eliminating the source of voltage imbalance
Solution Approach 2:
The common line is repositioned to a different spatial dimension - placed between the passivation layer and common electrode rather than between gate insulating layer and common electrode, changing the vertical stacking sequence to reduce dielectric thickness
Data Source
AI summary
In the present invention, a method for manufacturing a liquid crystal display is provided. The method includes steps of providing a substrate, forming a first metal layer on the substrate, etching the first metal layer to form a plurality of gate lines on the substrate, forming a common electrode on the substrate, forming a second metal layer on the substrate, etching the second metal layer to form a first electrode, a second electrode, a common line and a plurality of data lines on the substrate, and forming a pixel electrode overlapping the common electrode, wherein the gate lines intersect the data lines to form at least one enclosed area, the common electrode and the pixel electrode are positioned in the enclosed area, the first electrode is connected to the pixel electrode and the second electrode is connected to the data lines.