FFS LCD Fabrication via Diffraction Exposure
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Solution Overview
Problem
The existing fabrication methods for fringe field switching (FFS) mode liquid crystal display devices require multiple mask processes, leading to increased time and cost, and face challenges in maintaining exposure uniformity and photo-resist ashing uniformity due to diffraction-exposed regions.
Innovation Solution
A method that reduces the number of mask processes by using diffraction exposure to selectively remove gate metal, active layer, and source/drain regions, while forming source and drain electrodes, and involves a sequence of mask processes to form and pattern electrodes efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used to fabricate FFS mode LCD, then manufacturing precision is improved, but productivity deteriorates and cost increases
Solution Approach 1:
The patent combines multiple mask processes into a single mask process by using diffraction exposure to simultaneously form multiple electrode patterns (common electrode, gate line, data line, source electrode, and drain electrode) in one operation, thereby improving productivity while maintaining manufacturing precision through controlled diffraction patterns
2Productivity
If diffraction exposure is used to reduce mask processes, then productivity is improved, but exposure uniformity and photo-resist ashing uniformity deteriorate
Solution Approach 1:
The patent applies local quality by using different exposure conditions for different regions of the substrate. The diffraction exposure is applied selectively to form specific electrode patterns in particular areas, allowing optimized exposure parameters for each region while maintaining overall productivity benefits
Solution Approach 2:
The patent changes exposure parameters dynamically during the diffraction exposure process to maintain uniformity. By adjusting exposure time, intensity, and other parameters in real-time, the patent compensates for variations in diffraction exposure and achieves uniform photo-resist ashing while reducing the number of mask processes
3Object-affected harmful factors
If the area of diffraction exposure is minimized, then harmful effects are reduced, but device complexity increases
Solution Approach 1:
The patent segments the diffraction exposure process into multiple smaller exposure steps rather than one large exposure. By dividing the exposure area and using multiple diffraction patterns, the patent reduces the harmful effects of each individual exposure while achieving the complete electrode pattern, thereby balancing harmful effect reduction with process simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the area of diffraction exposure, reduces harmful effects, and improves manufacturing productivity and yield by reducing the number of mask processes, thereby lowering costs and enhancing fabrication efficiency.
Implementation Method 1
a method of fabricating a fringe field switching mode liquid crystal display device that reduces the number of mask processes using a diffraction exposure
Data Source
AI summary
A method of fabricating an FFS LCD is provided. The fabrication method comprises: forming a common electrode and gate metal on a board and etching them through a first mask process; forming a gate insulating layer, active layer and source/drain metal on the board; forming a channel in a TFT part, removing the gate metal in the pixel area part and opening a gate pad part; forming a passivation layer substantially on the board, and forming a contact hole on the TFT part, removing the active layer remaining from the pixel area part and exposing a gate pad part and a data pad part by a third mask process; and forming a pixel electrode substantially on the board, and forming a pixel electrode on regions contacting the drain electrode in the TFT part, having the opening in pixel area part and opened regions of the gate pad and data pad part through a fourth mask process.


