2D FFT Hardware Accelerator Pipeline Segmentation
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Solution Overview
Problem
Existing hardware accelerators, such as Radix-2 Single-Delay Feedback (R2SDF) pipelined architectures, are inefficient for two-dimensional (2D) Fast Fourier Transform (FFT) computations due to the need for multiple passes through the array, one for each dimension, which reduces the efficiency of the pipelined structure.
Innovation Solution
A hardware accelerator is designed with log2 M×N pipeline stages split into an initial group of log2 M stages and a final group of log2 N stages, allowing for a pipelined 2D FFT computation by performing an M-point 1D FFT in one direction and an N-point 1D FFT in the transposed direction, using control logic and twiddle factor addressing to efficiently process an M×N element array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing hardware accelerators use Radix-2 Single-Delay Feedback (R2SDF) pipelined architectures for 2D FFT computations, then the computational structure is simple and reusable, but multiple passes through the array are required which reduces processing efficiency
Solution Approach 1:
The hardware accelerator is segmented into two distinct groups of pipeline stages: an initial group performing M-point 1D FFT and a final group performing N-point 1D FFT. This segmentation allows each group to be optimized for its specific transform dimension while working together in a single pass to achieve 2D FFT computation, resolving the contradiction between processing efficiency and architectural simplicity.
Solution Approach 2:
The patent transitions from the conventional single-pass 1D FFT approach to a two-dimensional transformation by organizing pipeline stages into initial and final groups that handle different dimensions (M and N) of the 2D FFT. This dimensional organization enables simultaneous processing of both transform dimensions without requiring multiple passes, thereby improving productivity while managing complexity through structured design.
2Loss of time
If multiple passes through the hardware array are required for each dimension, then the hardware structure can be simpler and more reusable, but the processing time and idle time increase
Solution Approach 1:
The patent implements continuous useful action by organizing the pipeline stages so that data flows continuously through the initial group for M-point transform and then through the final group for N-point transform without interruption or idle passes. This continuous processing eliminates the idle time associated with multiple passes while managing complexity through the structured two-group organization of pipeline stages.
Solution Approach 2:
The initial group of pipeline stages performs preliminary M-point 1D FFT computation on the input data before it enters the final group for N-point transform. This preliminary action prepares the data in a form that enables the subsequent final transform to complete the 2D FFT in a single continuous pass, reducing idle time while organizing complexity into manageable sequential stages.
Data Source
AI summary
Devices, e.g., hardware accelerators, and systems are operable to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.