FFT Processor Conflict-Free Address Generation and Twiddle Factor Optimization
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Solution Overview
Problem
Existing FFT designs face challenges in memory access conflicts and resource efficiency due to the complexity of twiddle factor calculations and the need for concurrent butterfly operations, which limits the performance and throughput of FFT processors.
Innovation Solution
The use of multiple SRAMs and a conflict-free address generation scheme, combined with twiddle factor table reduction strategies, allows for concurrent butterfly operations without memory bank conflicts, optimizing memory access and reducing computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple butterfly units operate concurrently to increase throughput, then productivity is improved, but memory access conflicts increase causing device complexity to worsen
Solution Approach 1:
The memory system is segmented into multiple independent memory banks, allowing concurrent access by multiple butterfly units without conflicts. Each memory bank can be independently accessed, enabling parallel data retrieval for multiple butterfly operations simultaneously.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing memory access across multiple banks rather than sequentially within a single memory. This dimensional expansion allows multiple butterfly units to access different memory banks concurrently, eliminating access conflicts while maintaining high throughput.
2Area of stationary object
If minimal memory blocks are used to reduce area footprint, then area of stationary object is improved, but memory access conflicts increase causing productivity to worsen
Solution Approach 1:
The memory is divided into multiple smaller banks rather than using a single large memory block. This segmentation reduces the area required for each individual memory bank while enabling concurrent access patterns that maintain high throughput for multiple butterfly units.
Solution Approach 2:
Instead of expanding memory area horizontally with a single large block, the patent uses vertical parallelism by creating multiple memory banks that can be accessed simultaneously. This dimensional approach to memory organization achieves high throughput without proportionally increasing area footprint.
3Volume of stationary object
If twiddle factors are calculated on the fly to reduce memory usage, then volume of stationary object is improved, but device complexity worsens due to computational overhead
Solution Approach 1:
Rather than calculating all twiddle factors completely on the fly, the patent uses a hybrid approach where twiddle factors are pre-calculated and stored in compact form, then partially computed during operation. This reduces memory storage requirements while avoiding the excessive computational complexity of complete on-the-fly calculation.
Solution Approach 2:
The patent changes the representation parameters of twiddle factors, storing them in a compressed or transformed format that requires less memory. During operation, these parameters are efficiently converted to the required form, achieving reduced memory usage without excessive computational overhead.
Data Source
AI summary
A novel design for conflict free address generation mechanism is provided for reading data from Block RAM (BRAM) into a Fast Fourier Transform (FFT) module and writing back the processed data back to the BRAM. Also, a novel way of reducing a memory footprint by reducing a twiddle factor table size by taking an advantage of the symmetry property of twiddle factors is presented. Further, additional architecture-specific optimizations are provided, which involve a design of deeply pipelined butterfly modules and the BRAM accesses, parallel butterfly modules for a single FFT block and parallel FFT lane implementation.