FFT Circuit Address Logic for FPGA Resource Reduction
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Solution Overview
Problem
Conventional Fast Fourier Transform (FFT) circuits require significant resources and slow down due to the need for data reordering, which is critical and resource-intensive, especially in limited line resources like Field Programmable Gate Array (FPGA) designs.
Innovation Solution
A method and circuit that convert reversal-order or natural-order addresses to radix-based numeral representation, calculate sequence numbers for memory locations, and perform FFT/IFFT calculations using short DFT sequences, eliminating the need for reordering modules by utilizing modulo operations and cyclic shifts, allowing direct data input and output without additional memory or reordering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If data reordering is performed using selecting control logics for each butterfly calculation, then correct calculation order is achieved, but circuit area and speed are degraded due to resource consumption and critical path delays
Solution Approach 1:
The patent applies preliminary action by pre-reordering the input data into bit-reversal order before the FFT calculation begins. This eliminates the need for complex selecting control logics during each butterfly calculation stage, as the data is already in the correct order for processing. The address calculating unit computes memory addresses directly using bit-reversal logic, avoiding runtime reordering operations.
Solution Approach 2:
The patent extracts the reordering operation from the critical calculation path and performs it separately as a preliminary step. By separating the address calculation logic from the butterfly computation logic, the complex selecting control elements are removed from the data critical path, reducing both area and timing impact while maintaining calculation correctness.
2Manufacturing precision
If selecting control logics are used for reordering data in each butterfly calculation, then correct data sequence is maintained, but resource consumption increases significantly
Solution Approach 1:
The patent performs the reordering action preliminarily by organizing input data into bit-reversal order before processing. This single preliminary organization step replaces multiple selecting control logic operations that would otherwise be required at each calculation stage, significantly reducing resource consumption while maintaining data sequence accuracy.
Solution Approach 2:
The address calculating unit uses self-service by computing memory addresses directly through bit-reversal logic operations on the input address. This eliminates the need for external selecting control logics to manage data reordering, as the system serves itself by generating correct addresses through simple arithmetic operations rather than complex control elements.
3Manufacturing precision
If reordering operations are performed at each calculation stage, then correct FFT computation is achieved, but calculation speed decreases due to critical path delays
Solution Approach 1:
The patent performs the reordering action preliminarily before the main computation begins. By organizing data into bit-reversal order in advance, the critical calculation path is freed from reordering operations, allowing continuous computation without interruptions or delays associated with dynamic data resequencing at each stage.
Solution Approach 2:
The patent extracts the reordering operation from the critical calculation path and places it in a non-critical preliminary stage. This separation ensures that the time-consuming reordering operations do not delay the main FFT computation, as they are completed beforehand and the subsequent calculation stages proceed with data already in the correct order.
4Manufacturing precision
If complex reordering structures are implemented for limited line resources like FPGA, then correct data handling is achieved, but area and timing performance are significantly degraded
Solution Approach 1:
The address calculating unit employs self-service by generating correct memory addresses through bit-reversal logic operations performed directly on the address inputs. This eliminates the need for complex reordering structures that would consume significant FPGA line resources, as the system generates its own addressing information using simple, resource-efficient logical operations.
Solution Approach 2:
The patent substitutes mechanical reordering structures (physical data movement and switching elements) with logical address calculation operations. Instead of using complex selecting control logics that consume FPGA resources, the system uses arithmetic and logical operations on address bits to compute the correct memory locations, replacing resource-intensive mechanical reordering with efficient logical computation.
Data Source
AI summary
A FFT/IFFT method, comprises converting a set of reversal-order or a set of natural-order addresses of FFT/IFFT data to a set of addresses in a radix-based numeral representation; calculating sequence numbers of a plurality of memory locations for buffering a set of data for a parallel calculation, by accumulating or subtracting all digits of the set of addresses in the radix-based numeral representation and then performing a modulo operation on the accumulation or subtraction results, wherein the radix represents a length of short DFT sequence for the parallel calculation in a FFT/IFFT calculation; storing the FFT/IFFT data simultaneously and respectively into corresponding memory locations indicated by the calculated sequence numbers; and performing FFT/IFFT calculation, comprising: performing short DFT sequence calculation; repeating the short DFT sequence calculation, until the whole FFT/IFFT calculation completes.