Unified FFT Processor Algorithm Selection for RF Receiver Area Reduction
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Solution Overview
Problem
Conventional FFT processors are limited to operating only one Fourier algorithm, leading to increased cost and layout area in RF receivers designed to process different wireless specifications, as they require multiple processors for varying data sizes and specifications like UWB and WiMAX.
Innovation Solution
A unified FFT processor architecture that incorporates radix-2n, radix-2, and radix-23 algorithms, along with a multiplexer and bit-reverse circuit, enabling it to process both 2n and 2(n+1) point data, and switch between different algorithms based on data input, thereby reducing the need for multiple processors and optimizing layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single FFT processor is designed to handle multiple wireless specifications, then the adaptability and versatility improve, but the device complexity and layout area increase due to requiring multiple processors
Solution Approach 1:
The patent implements a unified FFT processor that can handle multiple wireless specifications (UWB, WiMAX, etc.) by integrating multiple algorithms (radix-2, radix-22, radix-23) within a single processor architecture. The processor uses algorithm selection logic to dynamically choose the appropriate algorithm based on the input data characteristics, eliminating the need for separate dedicated processors for each specification and thereby reducing hardware complexity while maintaining multi-specification support
2Adaptability or versatility
If radix-2 algorithm is used to process non-4n or non-8n point data, then the adaptability improves, but the number of complex number multipliers increases and layout area increases
Solution Approach 1:
The patent employs dynamic algorithm selection that adapts the FFT processing approach based on the input data size characteristics. When the input data size is suitable for radix-22 or radix-23 algorithms (4n or 8n points), these algorithms are selected to minimize the number of complex number multipliers and reduce layout area. When the data size does not fit these patterns, the processor dynamically switches to radix-2 algorithm, ensuring optimal resource utilization across all data sizes while maintaining adaptability
3Manufacturing precision
If different OFDM processors are designed for different wireless specifications, then the manufacturing precision for each specification improves, but the cost and layout area of the receiver increase
Solution Approach 1:
The patent creates a universal OFDM processor that maintains high processing accuracy for multiple wireless specifications by integrating specification-specific optimization within a unified architecture. The processor includes algorithm selection logic that identifies the appropriate wireless specification and selects the optimized algorithm (radix-2, radix-22, or radix-23) accordingly, ensuring manufacturing precision for each specification while using a single processor instance, thereby reducing the total number of processors required
Data Source
AI summary
An implement method of a FFT processor comprises the following steps. First, a 21 point FFT processor, which has an output and an input receiving a 2n+1 point data, is provided. A 2n-point FFT processor having an input and an output is provided. Sequentially, a multiplexer, which has a first input coupled to the output of the 21 point FFT processor, a second input receiving a 2n point data and an output coupled to the input of the 2n point FFT processor, is provided. When an input data is a 2n point data, the second input of multiplexer is coupled to the output thereof, and when an input data is a 2n+1 point data, the first input of multiplexer is coupled to the output thereof.