FFT Engine Bit-Reversal Layout for Low-Latency Memory Transpose
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Solution Overview
Problem
Existing FFT engines for multi-dimensional spectral analysis introduce significant latency due to separate transpose operations, which affect data processing efficiency and throughput.
Innovation Solution
A combined bit-reversal and memory transpose operation is integrated into the FFT engine topology, allowing simultaneous bit-reversal and memory transpose operations without additional latency, reducing the FFT engine footprint and improving data processing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If separate transpose operations are used in existing FFT engines, then bit-reversal and memory transpose operations can be performed independently, but data processing latency increases and throughput decreases
Solution Approach 1:
The patent combines bit-reversal permutation and memory transpose operations into a single unified operation. The memory interface is configured to perform both operations simultaneously by integrating the bit-reversal logic directly into the memory access pattern, eliminating the need for separate transpose operation circuits and reducing overall data processing latency.
Solution Approach 2:
The memory interface is designed to serve multiple functions: it performs both bit-reversal permutation and memory transpose operations, and can also handle standard memory read/write operations. This multi-functional design reduces the need for dedicated separate circuits for each operation, thereby reducing device complexity while maintaining processing efficiency.
2Productivity
If combined bit-reversal and memory transpose operations are integrated, then data processing latency is reduced, but the FFT engine footprint may increase
Solution Approach 1:
By merging bit-reversal and transpose operations into a single unified memory interface operation, the patent eliminates the need for separate operation circuits that would otherwise be required. This integration reduces the overall circuit area while achieving the dual functionality needed for efficient multi-dimensional FFT processing.
Solution Approach 2:
The unified memory interface is designed to handle multiple operations (bit-reversal, transpose, and standard memory access) through a single circuit structure. This multi-functional approach maximizes the utilization of the circuit area, achieving high productivity without proportionally increasing the FFT engine footprint.
Data Source
AI summary
An example system includes logic circuitry to receive digital signals and perform transform operations to generate N output samples for each of the digital signals, k output samples at a time, where k is an integer of 2 or greater and N is an integer multiple of k. Such system further includes circular shift circuitry that includes data multiplexers and address multiplexers to write respective sets of k output samples of the N output samples to k banks of a first memory. For each set of k output samples, the address multiplexers are used to generate k addresses that are bit-reversed with respect to the k output samples, and write a respective one of the k output samples at an indexed ordered position in a respective one of the k banks. The output samples are then read in linear address order from the k banks of the first memory and stored in transposed format in a second memory.