Single Buffer FFT Circuit for Address Order Switching

The patent merges the functionality of two separate buffers into a single buffer by implementing alternating buffer modes. The single buffer alternates between operating as a first buffer for natural address order data and a second buffer for bit-reversed address order data, eliminating the need for dual buffering infrastructure while maintaining the same data processing capability.

The patent employs periodic action by alternating the buffer's operational mode between natural address order and bit-reversed address order in a cyclic manner. The buffer toggles between serving as the first buffer and second buffer in alternating periods, allowing the same physical buffer to fulfill the roles of two separate buffers through time-division multiplexing.

The patent implements universality by designing a single buffer that can perform multiple functions - it can operate as either the first buffer for natural address order data or the second buffer for bit-reversed address order data depending on the operational phase. This multi-functionality allows the same logic resources to be reused alternately for different buffering tasks, significantly reducing the total quantity of logic resources required compared to dedicated dual buffering.

The patent combines the functionality of two separate buffers into one unified buffer structure, reducing the logic resources consumed by eliminating redundant buffering infrastructure. The merged buffer uses control logic to alternately serve both buffering roles, achieving FFT processing capability with fewer logic resources than traditional dual buffering approaches.