FFT Data Buffering With Delayed Write Address Reordering
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Solution Overview
Problem
Existing data buffering systems for FFT circuits face performance limitations due to dependencies between read and write operations, particularly when using memories with specific write modes and port configurations, which can reduce throughput and increase costs.
Innovation Solution
The implementation of a circuit with an address generator that applies a delay to write address signals relative to read address signals, allowing for independent read and write operations in a memory, enabling the use of dual-port memories with different write modes and improving system performance and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data buffering systems use memories with specific write modes and port configurations to reorder data, then data reordering functionality is achieved, but circuit performance is limited and throughput is reduced
Solution Approach 1:
The patent divides the memory system into two independent ports: a first port dedicated to write operations and a second port dedicated to read operations. This segmentation allows write and read operations to occur simultaneously without interfering with each other, eliminating the sequential dependency that limited throughput in conventional single-port memory systems.
Solution Approach 2:
The patent transitions from a single-port memory architecture to a dual-port memory architecture, adding a dimensional aspect to the memory access structure. This enables operations to proceed in parallel along the port dimension, effectively doubling the operational capacity and improving throughput by removing the sequential bottleneck.
2Productivity
If conventional data buffering systems use single-port memories with sequential operations, then device complexity is reduced, but throughput and performance are limited
Solution Approach 1:
The patent implements preliminary action by pre-configuring the memory with two independent ports before operations begin. The write port and read port are established in advance, allowing write operations to be initiated without waiting for read operations to complete, and vice versa. This preliminary structuring enables continuous parallel operations that maximize throughput.
Solution Approach 2:
The dual-port memory structure provides multi-functionality by enabling the same memory resource to serve two independent operations simultaneously. The first port handles write operations while the second port handles read operations, making the memory system universal in its ability to perform both functions without requiring separate memory units, thus improving throughput without proportionally increasing complexity.
3Adaptability or versatility
If data buffering systems require specific memory write modes, then data integrity is maintained, but design flexibility is reduced
Solution Approach 1:
The patent applies local quality by assigning different operational characteristics to different ports of the same memory system. The write port is configured for write operations with appropriate write enable signals and timing, while the read port is configured for read operations with appropriate read enable signals and timing. Each port has optimized local characteristics for its specific function, maintaining data integrity for that operation type while allowing the overall system to be highly adaptable to different design requirements.
Data Source
AI summary
A circuit includes a memory and an address generator configured to generate a write address signal and a read address signal, where the write address signal has a first delay relative to the read address signal. The memory is configured to receive a first plurality of write addresses, from the write address signal, including a first plurality of addresses of the memory in a first order, and write, to the first plurality of write addresses, a first plurality of data words during a first time period. The memory is further configured to receive a first plurality of read addresses, from the read address signal, including the first plurality of addresses in a second order, and read, from the first plurality of read addresses, the first plurality of data words during a second time period. The first and second time periods partially overlap. The first order may be one of a natural order and a modified order, with the second order being the other of the natural order and the modified order, and the modified order may be one of a bit-reversed order and a digit-reversed order. The memory may have different write modes, and may be a read-before-write memory or a write-before-read memory.