Multi-Granularity Parallel FFT Butterfly Computation

The patent divides the FFT computation into multiple stages and segments data access patterns. By organizing butterfly computations into stages where data is accessed once and reused across multiple butterfly operations, the system segments the computation to minimize repeated memory accesses. Each stage processes a specific portion of the data with optimized access patterns, reducing overall memory access delay while maintaining parallel throughput.

The patent implements preliminary data reorganization and buffering before the main parallel computation stages. Data is pre-arranged in memory buffers in an order that facilitates efficient parallel access during computation. Twiddle factors and input data are pre-loaded and organized so that during the parallel butterfly computation stages, processors can access data without causing memory access bottlenecks, thus reducing delay while maintaining high throughput.

The patent merges multiple memory access operations into single consolidated accesses. By combining the reading of data for multiple butterfly computations into a single memory read operation, and similarly combining write operations, the system reduces the total number of memory access transactions. This allows staged computation to proceed efficiently without the speed limitation imposed by frequent sequential memory accesses.

The patent ensures continuous data flow through the computation pipeline by maintaining data in intermediate buffers between stages. Instead of stopping computation to perform memory reads/writes at each stage boundary, the system keeps data continuously available in fast memory buffers, allowing parallel processors to maintain continuous useful action without interruption from memory access delays, thus preserving both staged computation capability and high speed.