Pipelined FFT Calculator Butterfly Unit Resource Sharing
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Solution Overview
Problem
Existing pipelined FFT architectures require significant memory and resources to implement multiple stages of the radix-22 DIF algorithm, leading to inefficiencies in area usage and computational throughput.
Innovation Solution
The proposed solution involves a pipelined FFT calculator with butterfly calculation units that share resources to perform simultaneous calculations for multiple stages of the FFT algorithm, reducing the number of required memory locations and computational units while maintaining high clock speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional pipelined FFT architectures are used to implement multiple stages of the radix-22 DIF algorithm, then computational functionality is achieved, but memory requirements and area usage increase significantly
Solution Approach 1:
The patent combines multiple butterfly calculation units into a single unified unit that can perform calculations for multiple stages simultaneously. This merging eliminates the need for separate memory units for each stage, reducing total memory requirements while maintaining the computational throughput needed for processing 1024-point FFT operations.
Solution Approach 2:
The butterfly calculation unit is designed as a universal resource that can be shared across multiple FFT stages. Instead of having dedicated memory and calculation units for each stage, a single butterfly calculation unit with shared memory serves multiple stages, reducing area usage while maintaining productivity through time-multiplexed operation.
2Ease of operation
If separate memory units are allocated for each butterfly calculation unit, then stage-specific data access is simplified, but the number of required memory locations increases
Solution Approach 1:
Multiple separate memory units are merged into a single shared memory unit that serves all butterfly calculation units. This consolidation reduces the total quantity of memory locations from what would be required for separate units while maintaining ease of operation through unified memory management and addressing schemes.
3Speed
If multiple butterfly calculation units are used to process different stages simultaneously, then computational speed is improved, but device complexity increases
Solution Approach 1:
Multiple butterfly calculation units are merged into a single multi-functional unit that processes different stages sequentially or in an interleaved manner. This merging reduces device complexity by eliminating redundant calculation units while maintaining high clock speeds through efficient resource utilization and pipelining techniques.
Solution Approach 2:
The single butterfly calculation unit dynamically reconfigures or switches between processing different FFT stages based on operational requirements. This dynamic operation allows the unit to maintain high speed performance across multiple stages without requiring static duplication of calculation units, thereby reducing overall device complexity.
Data Source
AI summary
A discrete Fourier transform calculation apparatus includes a plurality of multiplier units, and a plurality of butterfly calculation units. Each butterfly calculation unit is configured to perform simultaneous calculations for at least two stages of a fast Fourier transform (FFT) algorithm by using shared resources of the butterfly calculation unit. Each butterfly calculation unit includes a respective memory device to store input data for the corresponding at least two stages of the FFT algorithm, and a respective butterfly calculator coupled to the respective memory device. Each butterfly calculation unit also includes a respective controller coupled to the respective memory device and the respective butterfly calculator. The respective controller is configured to control the corresponding butterfly calculation unit to calculate the corresponding at least two stages of the FFT algorithm. The plurality of butterfly calculation units and the plurality of multiplier units are coupled in series.