FFT Circuit Using Butterfly Units for Multi-Length Processing
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Solution Overview
Problem
Existing FFT processors require multiple operation circuits corresponding to different radices, leading to increased circuit size and power consumption due to their inability to handle various FFT lengths efficiently.
Innovation Solution
A fast Fourier transform (FFT) circuit is designed with a series of butterfly operation units, each performing complex multiplication and subtraction, allowing for flexible operation across multiple FFT lengths without the need for multiple operation circuits, utilizing a signal sequence conversion unit, complex multiplication unit, and complex addition/subtraction unit to adapt to varying FFT lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple operation circuits corresponding to different radices are used to handle various FFT lengths, then the FFT processor can perform operations for multiple standards, but the circuit size increases and power consumption increases
Solution Approach 1:
The patent implements a universal FFT operation circuit that can handle multiple FFT lengths (64, 256, 1024, etc.) using a single set of butterfly operation units. The circuit achieves multi-functionality by dynamically configuring the number of operation stages and selecting appropriate operation circuits based on the required FFT length, eliminating the need for separate dedicated circuits for each FFT length while maintaining full operational capability across different standards
Solution Approach 2:
The patent employs dynamic configuration of the FFT operation circuit by selectively activating a specific number of butterfly operation units and stages based on the required FFT length. The control unit dynamically adjusts the operational parameters including the number of complex multiplication units, complex addition/subtraction units, and the depth of the butterfly operation network, allowing the same hardware to adapt to different FFT lengths without physical reconfiguration
2Adaptability or versatility
If multiple operation circuits corresponding to different radices are used to handle various FFT lengths, then the FFT processor can perform operations for multiple standards, but power consumption increases
Solution Approach 1:
The patent implements a universal FFT operation circuit that can handle multiple FFT lengths (64, 256, 1024, etc.) using a single set of butterfly operation units. The circuit achieves multi-functionality by dynamically configuring the number of operation stages and selecting appropriate operation circuits based on the required FFT length, eliminating the need for separate dedicated circuits for each FFT length while maintaining full operational capability across different standards
Solution Approach 2:
The patent implements power-saving mechanisms by selectively deactivating unused butterfly operation units and stages when processing smaller FFT lengths. The control unit dynamically disables portions of the circuit that are not needed for the current operation, allowing the system to recover power that would otherwise be consumed by always-on dedicated circuits for all possible FFT lengths
3Device complexity
If a single set of butterfly operation units is used to handle multiple FFT lengths, then circuit size is reduced, but the circuit must be dynamically reconfigured for different operations
Solution Approach 1:
The patent implements a self-service configuration mechanism where the control unit automatically determines the appropriate FFT operation parameters based on the input signal characteristics and required processing. The system self-configures the number of butterfly operation units, stages, and connection patterns without requiring manual intervention, reducing the operational burden while maintaining the ability to handle multiple FFT lengths with a single circuit
Data Source
AI summary
A circuit for a fast Fourier transform (FFT) operation is provided. The FFT operation circuit includes a plurality of butterfly operation units connected in series. Each of the plurality of butterfly operation units reads a signal in the order in which the plurality of butterfly operation units perform complex multiplication, addition, and subtraction, performs complex multiplication of each sequentially read signal by a complex coefficient corresponding to an FFT length and the stage number of the butterfly operation unit, and performs complex addition and subtraction with the complex multiplied signal. In this way, without disposing a plurality of operation circuits corresponding to a radix, FFT operations corresponding to a plurality of FFT lengths can be performed.


