FFT Accelerator Clock Sequencing for Load Jump Mitigation
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Solution Overview
Problem
The Fast Fourier Transform (FFT) accelerator experiences load jumps and voltage fluctuations when a global clock is enabled, leading to potential malfunction or circuit damage due to increased current consumption, necessitating effective power supply reinforcement.
Innovation Solution
The proposed solution involves sequencing the clock to each circuit processing stage in a pipeline configuration, gradually increasing and decreasing power consumption to mitigate load jumps, using clock gate circuits and stage clock control circuits to enable or disable stage clock signals based on valid data receipt and processing delays, and employing partial shutdown or 'dream sleep' modes to manage power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a global clock is enabled to start processing in a parallel streaming FFT accelerator, then processing operation is initiated, but load jump or significant increase in current consumption occurs causing voltage drop and potential malfunction
Solution Approach 1:
The patent applies preliminary action by enabling clock signals to circuit processing stages in a predetermined sequence rather than simultaneously. The clock control circuits activate stages one by one according to a predefined order, allowing the system to gradually ramp up power consumption and avoid sudden load jumps that cause voltage drops and malfunction.
2Reliability
If the clock is turned off to prevent load jump, then current consumption is reduced, but overvoltage and circuit damage may occur
Solution Approach 1:
The patent applies dynamics by implementing bidirectional clock sequencing - both enabling and disabling clock signals in a controlled sequential manner. When shutting down, the clock control circuits disable stages in reverse sequence, gradually reducing power consumption and preventing sudden current drops that would cause overvoltage and potential circuit damage.
3Speed
If all circuit processing stages are clocked simultaneously, then processing speed is maximized, but load jump occurs due to abrupt power consumption increase
Solution Approach 1:
The patent applies segmentation by dividing the simultaneous clocking of all circuit processing stages into sequential segments. Instead of enabling all stages at once, the clock control circuits activate them in predetermined groups or individually over multiple clock cycles, segmenting the power consumption increase to avoid abrupt load jumps while still achieving full processing throughput.
Data Source
AI summary
A circuit having load jump mitigation, including: circuit processing stages arranged in a pipeline configuration and operable based on respective stage clock signals; and clock control circuits respectively connected to the circuit processing stages to control the respective stage clock signals. Each of the clock control circuits is operable to: enable the respective stage clock signal in response to receiving a data in signal representing that the respective circuit processing stage begins to receive valid data for processing; disable the respective stage clock signal based on a predetermined respective circuit processing stage processing delay having elapsed since the respective circuit processing stage received any valid data; and enable a next of the clock control circuits, which is connected to a next of the circuit processing stages, based on the predetermined respective circuit processing stage processing delay having elapsed since the respective stage clock signal was enabled, indicating that the respective circuit processing stage is beginning to send the processed valid data to the next circuit processing stage.