FFT Data Reordering via Address Bit Permutation
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Solution Overview
Problem
Radix 4n2m FFT operations require data reordering, which typically necessitates two memory banks, leading to inefficient memory utilization and increased latency due to the need for storing and reordering data items from non-natural to natural order.
Innovation Solution
The use of dual-port memory circuitry with address signals reordered to allow storage and retrieval of data items in a single memory bank, utilizing address bit permutation to achieve efficient reordering of data items from non-natural to natural order, reducing memory requirements and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If two memory banks are used to store and reorder data items, then data reordering from non-natural to natural order can be achieved, but memory utilization becomes inefficient and latency increases
Solution Approach 1:
The patent segments the memory access operation into two distinct phases: a first phase where data items are stored in memory locations according to non-natural order addresses, and a second phase where the same memory locations are accessed in natural order. This temporal segmentation allows a single memory bank to perform the reordering function that traditionally required two memory banks, thereby reducing memory requirements while maintaining the data reordering capability.
2Ease of operation
If two memory banks are used to store and reorder data items, then data reordering from non-natural to natural order can be achieved, but latency increases
Solution Approach 1:
The patent segments the memory access operation into two distinct phases: a first phase where data items are stored in memory locations according to non-natural order addresses, and a second phase where the same memory locations are accessed in natural order. This temporal segmentation allows a single memory bank to perform the reordering function that traditionally required two memory banks, thereby reducing memory requirements while maintaining the data reordering capability.
Solution Approach 2:
The patent performs preliminary storage of all required data items in a single memory bank during the first phase before the actual retrieval operation begins. By having all data items pre-positioned in the memory bank with appropriate addressing, the system eliminates the need for additional memory access latency that would occur with multi-bank switching or complex reordering operations during the retrieval phase.
3Quantity of substance
If address signals are reordered for each successive set of N data signal items, then efficient memory utilization is achieved, but address signal processing complexity increases
Solution Approach 1:
The patent employs address conversion logic that generates natural order address signals as a transformed copy of the non-natural order addresses. Instead of physically reordering data items or using complex routing, the system creates a parallel set of address signals that map to the same memory locations but in the desired natural order, thereby simplifying the overall system architecture while achieving efficient memory utilization.
Data Source
AI summary
Data signal items output by a radix 4n2m fast Fourier transform (“FFT”) operation may not be in the order desired for further use of those data items (e.g., they may be output in a non-natural order rather than in a desired natural order). Memory circuitry (e.g., dual-port memory circuitry) may be used in conjunction with circuitry for addressing the memory circuitry with address signals that are reordered in a particular way for each successive set of N data items. This allows use of memory circuitry with fewer data item storage locations than would otherwise be required to reorder the data items from non-natural to natural order. In particular, the memory circuitry only needs to be able to store N data items at any one time, which is more efficient memory utilization than would otherwise be possible.