FFT Device Data Sorting for Latency Reduction
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Solution Overview
Problem
Existing FFT devices suffer from increased processing latency and circuit complexity due to inefficient output timing and order of frequency-domain signals, which hinders the speedup of subsequent processing stages and leads to higher power consumption.
Innovation Solution
A fast Fourier transform device with a data sorting processing unit that rearranges output data to optimize their order for subsequent stages, allowing for simultaneous or near-simultaneous processing of signals, reducing the need for additional circuitry and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If FFT processing is performed by decomposing into smaller FFTs using the prime factor method, then the circuit complexity is reduced, but the processing latency increases due to sequential execution of multiple stages
Solution Approach 1:
The FFT processing is segmented into multiple stages (first stage, second stage, etc.) where each stage performs a portion of the overall transformation. This segmentation allows the circuit to be divided into manageable blocks that can be executed sequentially, reducing the complexity of any single circuit while maintaining the complete FFT functionality through staged processing.
Solution Approach 2:
Data sorting processing is performed in advance before each FFT stage to arrange input data in the optimal order for that stage's computation. This preliminary arrangement of data ensures that subsequent processing stages can proceed efficiently without requiring additional rearrangement operations, thereby minimizing overall processing latency despite the segmented approach.
2Productivity
If data sorting processing is added to optimize output order for subsequent stages, then the processing speed of subsequent stages is improved, but the device complexity increases
Solution Approach 1:
The data sorting processing is merged with the FFT processing stages rather than being implemented as separate, independent sorting circuits. The sorting operations are integrated into the data flow between stages, allowing the same hardware resources to perform both sorting and transformation functions, thereby improving subsequent stage processing speed without proportionally increasing overall device complexity.
Solution Approach 2:
The FFT processing circuit is designed to perform multiple functions: it not only executes the Fourier transformation but also inherently performs data sorting and rearrangement operations required for optimal processing order. This multi-functionality allows a single circuit to achieve both transformation and optimization goals without requiring additional dedicated sorting hardware, thus improving productivity while controlling device complexity.
3Productivity
If multiple stages of butterfly computation are used to achieve high-speed processing, then the processing throughput increases, but the circuit scale and power consumption increase
Solution Approach 1:
The high-speed FFT processing is achieved by segmenting the computation into multiple sequential stages, each handling a portion of the total transformation. This segmentation allows the circuit scale of each individual stage to remain manageable while the cumulative effect of multiple stages achieves the desired high processing throughput, avoiding the need for a single large-scale circuit that would consume excessive power.
Solution Approach 2:
The multiple stages of butterfly computation are designed to operate in a continuous pipeline where output from one stage immediately becomes input to the next stage. This continuous operation maximizes the utilization of circuit resources across all stages, ensuring that the increased circuit scale is justified by sustained high processing throughput rather than idle capacity, thereby optimizing the trade-off between circuit scale and productivity.
Data Source
AI summary
A fast Fourier transform device comprises: a first transform means including a first butterfly computation processing means that performs butterfly computation processing and outputs a plurality of sets of first output data in a first order; and a first data rearrangement processing means. The first butterfly computation processing means includes a plurality of radix-n butterfly computation processing means (where n is a multiple of 2), the number of the plurality of radix-n butterfly computation processing means being more than or equal to the number of the plurality of sets, and the plurality of sets of the first output data are output in the first order from the plurality of radix-n butterfly computation processing means.