FFT Device Power Reduction via Cycle Interleaving
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Solution Overview
Problem
Existing Fast Fourier Transform (FFT) circuits face high power consumption due to inefficient ordering of repetitive processes, which is not effectively addressed by previous technologies.
Innovation Solution
A Fast Fourier Transform device and method that performs FFT/IFFT processes in M cycles, utilizing data sorting and twiddle multiplication units to optimize the processing order, reducing power consumption by interleaving processing cycles and minimizing dynamic power consumption through specific output orders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If FFT/IFFT processes are performed sequentially in conventional order, then processing is simpler to implement, but power consumption increases due to inefficient operational rates
Solution Approach 1:
The patent applies preliminary action by performing data sorting operations before the FFT/IFFT processing to arrange input data in an optimal order (bit-reversed order). This preliminary arrangement enables more efficient processing cycles and reduces power consumption during the actual transform operations, as the data is already positioned to minimize computational overhead in subsequent stages
Solution Approach 2:
The patent implements periodic action by dividing the FFT/IFFT processing into M consecutive cycles, where each cycle processes a subset of data points. This periodic structure allows for optimized operational rates within each cycle while maintaining overall processing efficiency, reducing power consumption through rhythmic, controlled processing intervals rather than continuous operation
2Loss of energy
If data is processed in conventional sequential order, then implementation is straightforward, but dynamic power consumption increases due to suboptimal operational rates
Solution Approach 1:
The patent applies dynamics by implementing variable operational rates across different processing cycles. Instead of a fixed sequential processing order, the system dynamically adjusts the processing rate and data flow timing in each of the M cycles to optimize power efficiency. This dynamic approach allows the circuit to operate at lower average power levels while maintaining throughput requirements
Solution Approach 2:
The patent performs preliminary data sorting and reordering operations before the main processing stages to arrange data in an optimal sequence. This preliminary action reduces the computational complexity and power requirements during the actual FFT/IFFT computation, as the data is pre-positioned to minimize memory access patterns and arithmetic operations in the critical processing path
3Use of energy by moving object
If conventional processing order is used, then circuit implementation is simpler, but power consumption increases due to inefficient cycle management
Solution Approach 1:
The patent structures the FFT/IFFT processing as M consecutive cycles with periodic execution patterns. Each cycle processes a specific portion of the data with optimized timing and operational rates. This periodic structure improves power efficiency by allowing the circuit to enter lower-power states between cycles while maintaining high processing efficiency within each active cycle, achieving both energy savings and productivity
Solution Approach 2:
The patent segments the overall FFT/IFFT processing into M distinct consecutive cycles, where each cycle handles a specific subset of computations. This segmentation allows independent optimization of each cycle's power consumption and processing efficiency, enabling the system to achieve lower overall power usage while maintaining or improving total processing throughput through parallelizable cycle structures
Data Source
AI summary
When performing a fast Fourier transform or an inverse fast Fourier transform in M cycles on input data in units of N consecutive input data, an FFT device, in F fast Fourier transforms or F inverse fast Fourier transforms, sorts (F×N) first input data in a first order to output first output data in a second order, performs a butterfly computation process on the first output data to output second output data in the first order, sorts the second output data to output third output data in a third order, and performs a twiddle multiplication process on the third output data to output fourth output data in the third order, and the third order is an order in which processes of the Cth cycle in the F fast Fourier transforms or the F inverse fast Fourier transforms are performed in a consecutive cycle.