FFT-DRAM Cell With Integrated Trench Capacitor for Logic ICs
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Solution Overview
Problem
Current high-performance transistor technologies for MOS VLSI around 28 nm are complex and costly to manufacture, making it difficult to integrate dynamic random access memory (DRAM) cells into integrated circuit chips, leading to separate DRAM chips and increased size, power consumption, and cost in IoT applications.
Innovation Solution
The integration of a Flat Field Transistor (FFT) based dynamic random-access memory (DRAM) technology, which includes an epitaxially grown source region and a trench capacitor, reducing threshold voltage variability and allowing for low-cost, high-performance DRAM integration into logic or processing ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET technology is used for high-performance MOS VLSI fabrication, then transistor performance is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent employs planar transistor structures with simplified fabrication processes instead of complex FinFET architectures, accepting slightly reduced performance in exchange for dramatically lower manufacturing complexity and cost, making the devices more suitable for cost-sensitive applications
Solution Approach 2:
The patent modifies key transistor parameters such as channel width, length, and doping concentrations to optimize performance within the constraints of planar fabrication, achieving acceptable transistor characteristics without requiring advanced FinFET manufacturing processes
2Speed
If DRAM cells are integrated into IoT ICs/SOCs, then access speed is improved, but processing complexity and manufacturing cost increase
Solution Approach 1:
The patent integrates DRAM cells directly into the IoT IC/SOC using the same planar fabrication process for both logic and memory, merging the manufacturing processes to eliminate the need for separate DRAM chip fabrication and assembly, thereby reducing overall processing complexity
Solution Approach 2:
The patent uses a universal planar transistor design that can serve both as logic transistors and as DRAM access transistors, allowing the same fabrication process to produce both compute and memory functions, simplifying the overall manufacturing workflow
3Quantity of substance
If multiple separate DRAM chips are used, then memory capacity is achieved, but device size and power consumption increase
Solution Approach 1:
The patent combines multiple DRAM cell arrays and logic circuits onto a single IoT IC/SOC substrate, merging what would otherwise require multiple separate chips into one integrated device, thereby reducing overall device size and eliminating the need for chip-to-chip interconnects
Solution Approach 2:
The patent embeds DRAM cells within the same IC substrate as the logic circuits, nesting memory functionality inside the processing chip rather than requiring external memory chips, which reduces the overall system footprint and eliminates additional packaging layers
4Quantity of substance
If full DRAM chip is attached to IC/SOC for small memory needs, then memory capacity is satisfied, but product cost increases
Solution Approach 1:
The patent segments the memory capacity into small, modular DRAM cell arrays that can be precisely sized to match the specific memory needs of each IoT application, allowing customization of memory capacity rather than requiring a full DRAM chip attachment, thereby optimizing product cost
Solution Approach 2:
The patent provides localized memory integration where small DRAM arrays are embedded directly next to the logic circuits that need them, allowing each region of the IC to have its memory requirements satisfied locally without requiring a full external DRAM chip, reducing overall system cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables low-cost, high-performance DRAM integration with reduced power consumption and increased access speed, suitable for IoT applications, while maintaining noise margins and optimizing array architecture.
Implementation Method 1
a trench capacitor structurally integrated into the epitaxially grown source region
Implementation Method 2
When the FFT-DRAM is turned on, the first terminal of the capacitor is connected to a bit line connected to a drain of the FFT-DRAM
Data Source
AI summary
A flat field transistor (FFT) based dynamic random-access memory (DRAM) (FFT-DRAM) is disclosed. The FFT-DRAM comprises an epitaxially grown source region comprising a source extension and an epitaxial source over and in contact with the source extension. The epitaxially grown source region is over a surface of a semiconductor substrate. The FFT-DRAM further comprises a trench capacitor structurally integrated into the epitaxially grown source region. The trench capacitor has a first terminal formed by the epitaxially grown source region and a second terminal being a conductive material filling one or more trenches of the trench capacitor. The second terminal is connected to a ground terminal or a fixed voltage terminal.