FFT IFFT Processor Butterfly Operation Contiguous Storage
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Solution Overview
Problem
Existing FFT/IFFT processors face inefficiencies due to high computational complexity and memory load/store bottlenecks, leading to increased time and silicon area requirements, especially for large values of N, as they require numerous multiplications and additions, and conventional methods like radix-2 or radix-4 approaches are costly and complex.
Innovation Solution
An improved FFT/IFFT processor design that allows simultaneous processing and storage of multiple consecutive butterfly operations by using an address generator to construct addresses with '0' or '1' bits, augmented data buses, and registers to access and process operands in contiguous memory locations, reducing the need for multiple load/store units and enhancing computational throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional radix-2 or radix-4 FFT/IFFT methods are used, then the transform can be computed with reduced complexity compared to direct DFT, but the processor still requires multiple load/store units and has memory access bottlenecks that limit throughput
Solution Approach 1:
The patent segments the FFT/IFFT computation into multiple stages, with each stage processing a subset of butterflies. The input sequence is divided into groups, and each group is processed by a separate butterfly processing unit. This segmentation allows parallel processing of multiple butterfly operations simultaneously, increasing throughput without requiring a proportional increase in load/store units, as the memory access patterns are optimized for the segmented structure.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing butterflies into stages and groups, rather than processing them sequentially or in simple parallel batches. The multi-dimensional organization (stages × groups × butterflies per group) allows efficient utilization of memory bandwidth and computational resources, achieving high throughput with a limited number of load/store units by exploiting temporal and spatial reuse of data across different processing dimensions.
2Productivity
If multiple load/store units are provided to enable simultaneous loading of operands for multiple butterflies, then computational throughput increases, but silicon area and device complexity increase significantly
Solution Approach 1:
The patent ensures continuous utilization of the limited load/store units by optimizing the data flow and memory access patterns across stages and groups. The segmented butterfly processing is arranged so that load/store operations are pipelined and overlapped with computational operations, eliminating idle time for memory units. This continuous action allows the processor to achieve high throughput with fewer load/store units, reducing silicon area while maintaining productivity.
Solution Approach 2:
The patent employs preliminary organization of input data into groups and pre-computation of certain values (such as twiddle factors or intermediate results) that can be reused across multiple butterflies. This preliminary action reduces the number of memory accesses required during the main computation phase, allowing the use of fewer load/store units without compromising throughput, thereby reducing silicon area.
3Ease of operation
If inputs/outputs of consecutive butterflies are stored in non-contiguous memory locations, then the conventional butterfly computation can proceed, but loading/storing operands requires multiple separate operations and reduces efficiency
Solution Approach 1:
The patent merges multiple butterfly operations into stages and groups, and organizes their memory addresses so that operands for multiple butterflies within the same stage and group are stored in contiguous or closely spaced memory locations. This merging allows a single load/store operation to fetch or store data for multiple butterflies simultaneously, greatly improving loading/storing efficiency. The address generation logic is designed to produce sequential or predictable address patterns that exploit spatial locality in memory.
4Loss of time
If the number of arithmetic operations is reduced using FFT algorithms, then computation time decreases compared to direct DFT, but the requirement for optimized memory access and parallel processing increases device complexity
Solution Approach 1:
The patent employs a dynamic processor architecture where the configuration of butterfly processing units, stages, and groups can be adapted to different FFT/IFFT sizes and requirements. The processor can dynamically reconfigure the number of active processing units, the depth of the pipeline, and the grouping strategy based on the input size and performance requirements. This dynamic adaptability allows the processor to achieve optimal computation time for various workloads without requiring a fixed complex architecture for the worst-case scenario, thus balancing performance and complexity.
Data Source
AI summary
An FFT/IFFT processor having computation logic capable of processing butterfly operations, and storage for storing the operands of butterfly operations, including a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations and wherein the computation logic is capable of simultaneously accessing and processing said multiple butterfly operations.