Multiprocessor FFT/IFFT Computation with Reduced Inter-Processor Communication
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Solution Overview
Problem
Current multiprocessing implementations of FFT/IFFT do not provide linear scalability in computation time reduction with an increase in the number of processors due to high inter-processor communication overhead and inefficient data distribution, leading to suboptimal performance in high-speed and real-time applications.
Innovation Solution
A method and system for implementing FFT/IFFT in multiprocessor architectures that eliminates inter-processor communication after the first log2P stages by computing each butterfly stage on either a single processor or multiple processors simultaneously, with subsequent stages distributed among processors such that each chain of cascaded butterflies is processed by the same processor, using address generation techniques to assign operand addresses and compute twiddle factors efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional multiprocessing implementations of FFT/IFFT are used, then computation time is reduced with multiple processors, but inter-processor communication overhead increases and linear scalability is lost
Solution Approach 1:
The patent segments the FFT/IFFT computation into distinct stages, with the first log2P stages processed by multiple processors in parallel and subsequent stages processed sequentially by a single processor. This segmentation eliminates the need for continuous inter-processor communication while maintaining computational efficiency, as each processor handles independent butterfly operations within its assigned stage without requiring data exchange with other processors.
2Productivity
If more processors are added to reduce computation time, then throughput improves, but inter-processor data communication requirements increase
Solution Approach 1:
The patent performs preliminary distribution of input data to multiple processors before the computation begins, with each processor receiving and storing the specific data segments it will need for its assigned stages. This preliminary action eliminates the need for ongoing data communication during computation, as all required data is locally available to each processor when needed, thereby maintaining high throughput without increasing communication overhead.
3Device complexity
If FFT/IFFT is implemented on a single processor, then inter-processor communication is eliminated, but computation time increases and throughput decreases
Solution Approach 1:
The patent employs a dynamic processing model where the system transitions from using multiple processors for the first log2P stages to using a single processor for subsequent stages. This dynamic approach allows the system to maximize parallel processing capability when it provides the greatest benefit (early stages with high computational load) and then transition to sequential processing when communication overhead would diminish returns (later stages), thereby optimizing throughput without unnecessary communication complexity.
Data Source
AI summary
The embodiments of the present invention provide a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first “log2P” stages for an implementation using “P” processing elements, comprising computing each butterfly of the first “log2P” stages on either a single processor or each of the “P” processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the “P” processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor. The embodiments of the invention also provide a system for obtaining scalable implementation of FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first “log2P” stages for an implementation using “P” processing elements.