Fixed Point FFT Instruction Set for Hardware Efficiency
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Solution Overview
Problem
Fast Fourier Transform (FFT) algorithms incur high hardware costs due to non-sequential data movement and long data-dependent chains, and fixed point operations compromise precision.
Innovation Solution
A computer-implemented method and system providing an instruction set for a fixed point processor architecture that includes a small set of instructions to efficiently implement FFT algorithms, utilizing vector register files and scratch state memory for input data, and employing dynamic scaling to enhance accuracy without performance overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed point operations are used in FFT algorithms, then hardware cost is reduced, but output precision deteriorates
Solution Approach 1:
The patent implements dynamic scaling factors that are adjusted during FFT computation based on the accumulated error magnitude. This dynamic adjustment allows the fixed-point system to maintain precision by adapting the scaling behavior to the actual computational needs, rather than using static fixed-point arithmetic throughout.
Solution Approach 2:
The patent changes the parameter of scaling from fixed to dynamic during computation. By introducing dynamically adjustable scaling factors that modify the fixed-point arithmetic behavior based on runtime conditions, the system achieves both hardware efficiency and improved precision output.
2Productivity
If vector operations are used in FFT algorithms, then computation speed is improved, but hardware cost increases
Solution Approach 1:
The patent segments the FFT computation into distinct phases: data reorganization using vector operations, followed by butterfly computations using fixed-point operations with dynamic scaling. This segmentation allows vector operations to be used only where they provide benefit (data movement and reorganization) while using simpler fixed-point operations for the computationally intensive butterfly stages.
Solution Approach 2:
The patent creates a hybrid architecture where the processing unit can operate in multiple modes - vector operations for data reorganization and fixed-point operations with dynamic scaling for butterfly computations. This multi-functionality allows the same hardware to efficiently handle different types of operations with appropriate methods.
3Measurement precision
If dynamic scaling is implemented, then accuracy is improved, but computational overhead increases
Solution Approach 1:
The patent applies dynamic scaling selectively - not at every computation step, but only when needed based on error magnitude thresholds. This partial application of scaling reduces the computational overhead compared to applying scaling uniformly throughout the entire FFT computation, while still maintaining accuracy where required.
Data Source
AI summary
A computer implemented method and system for providing a Fast Fourier Transform (FFT) capability to a fixed point processor architecture is disclosed. In a first aspect the computer implemented method and system comprises providing an instruction set within the fixed point architecture. The instruction set includes a plurality of instructions to calculate at least one set of add operations within a FFT butterfly. The plurality of instructions are controlled by a mode register, wherein a plurality of vector register files and a scratch state memory provide input data to at the at least one set of add operations.