FFT Memory Transpose Using Combined Bit-Reversal Addressing
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Solution Overview
Problem
Existing Fast Fourier Transform (FFT) engine topologies for multi-dimensional spectral analysis introduce significant latency and require additional circuit area due to separate transpose operations, which hinder high-throughput applications like radar data processing.
Innovation Solution
The implementation of a data processing device with combined bit-reversal and memory transpose operations in the FFT engine, utilizing circular shift components to write FFT output samples in bit-reversed order and read them in linear order for storage in a second memory device, thereby eliminating the need for extra latency-inducing transpose operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate transpose and bit-reversal operations are implemented in existing FFT engine topologies, then the FFT operations can be performed, but significant latency and increased integrated circuit area are incurred
Solution Approach 1:
The patent combines the transpose operation and bit-reversal operation into a single unified operation. The memory interface performs both operations simultaneously by writing FFT output samples directly into memory locations that are both transposed and bit-reversed, eliminating the need for separate operation stages and reducing processing latency
Solution Approach 2:
The bit-reversal addressing is pre-calculated and integrated into the memory write address generation. The memory interface uses bit-reversed address ordering from the outset, so that when samples are written in transpose order, they automatically end up in the correct final positions without requiring subsequent reordering operations
2Productivity
If separate transpose and bit-reversal operations are implemented in existing FFT engine topologies, then the FFT operations can be performed, but increased integrated circuit area is incurred
Solution Approach 1:
The patent merges the transpose operation and bit-reversal operation into a single unified operation. The memory interface performs both operations simultaneously by writing FFT output samples directly into memory locations that are both transposed and bit-reversed, eliminating the need for separate operation stages and reducing integrated circuit area
Solution Approach 2:
The memory interface is designed to perform multiple functions: it handles data transfer between FFT logic and memory, performs transpose operations, and implements bit-reversal addressing. This multi-functional design eliminates the need for dedicated separate hardware blocks for each operation, reducing overall circuit area
3Loss of time
If FFT output samples are written in bit-reversed order and read in linear order using combined operations, then latency and footprint are reduced, but the memory access pattern becomes more complex
Solution Approach 1:
The patent introduces a bit-reversed address generator as an intermediary component that translates linear memory addresses into bit-reversed addresses for the memory interface. This mediator handles the complexity of bit-reversal addressing, allowing the rest of the system to operate with simple linear addressing while still achieving the benefits of combined operations
Data Source
AI summary
A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.