Multi-granularity Parallel FFT Device with Conflict-free Memory Access
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Solution Overview
Problem
Existing parallel FFT algorithms face inefficiencies in memory access and computation due to data length and read/write granularity variations, leading to conflicts and complex address calculations, especially when dealing with different data lengths and read/write granularities.
Innovation Solution
A multi-granularity parallel FFT computation device with multiple memories and a state control unit that generates read/write addresses and control signals, allowing for parallel computation of butterfly groups and twiddle factors, and performing bit-reversal operations simultaneously with read/write operations, eliminating memory conflicts and sorting requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors are used to compute short FFT sequences in parallel, then computation speed is improved, but memory access conflicts and synchronization complexity increase
Solution Approach 1:
The patent segments the FFT computation into multiple independent processing elements (PEs), each handling a specific portion of the computation. Each PE is assigned a unique identifier that determines its access pattern to the shared memory, allowing parallel execution without conflicts. The segmentation of both computation and memory access patterns enables multiple processors to work simultaneously on different data segments.
Solution Approach 2:
The patent introduces a new dimension of control by using the processor identifier as an additional index dimension for memory access. Instead of having all processors compete for the same memory addresses, each processor ID maps to a specific memory address space or access pattern, effectively adding a dimensional layer to the memory addressing scheme that eliminates conflicts while maintaining parallelism.
2Reliability
If dedicated memories and data buffers are used for each processor, then memory access conflicts are eliminated, but device complexity and implementation difficulty increase
Solution Approach 1:
The patent implements a universal shared memory structure that serves all processing elements simultaneously. The same memory array is used by all PEs, but each PE accesses it according to a unique pattern determined by its identifier. This multi-functional memory design eliminates the need for dedicated memories for each processor while preventing access conflicts through coordinated access patterns.
Solution Approach 2:
The patent changes the access parameters (address calculation formulas, timing, and pattern) based on the processor identifier. Each processor uses different address generation parameters when accessing the shared memory, allowing simultaneous access without conflicts. This dynamic parameter adjustment based on processor ID enables conflict-free parallel access to a shared resource.
3Productivity
If FFT data are sorted using multiple data buffers and selectors, then parallel read/write is achieved, but calculation of R/W addresses becomes complex and implementation becomes difficult
Solution Approach 1:
The patent enables each processing element to self-determine its memory access addresses using simple arithmetic operations based on its own identifier and the current computation stage. Each PE calculates its own read and write addresses without requiring complex centralized address management or multiple buffer sorting structures. This self-service address calculation dramatically simplifies the control logic while maintaining parallel access capability.
4Manufacturing precision
If bit-reversal sorting is performed separately before computation, then data is properly organized for FFT, but additional processing time and memory access are required
Solution Approach 1:
The patent merges the bit-reversal sorting operation with the main FFT computation by integrating it into the first computation stage. Instead of performing bit-reversal as a separate preprocessing step, the patent incorporates it into the butterfly operations of stage 0, where the natural data flow and computation structure already support the reordering. This merging eliminates the need for separate sorting passes and reduces total processing time.
Solution Approach 2:
The patent performs the bit-reversal reordering as part of the initial data loading and first computation stage setup, preparing the data in the correct order before the main computational phases begin. By anticipating the required data arrangement and incorporating it into the earliest possible stage of computation, the patent avoids later reordering operations and ensures data is properly organized from the start of the computational process.
Data Source
AI summary
A multi-granularity parallel FFT computation device including three memories, a butterfly computation device, a state control unit, a data reversing network and a first selector. The three memories are each a multi-granularity parallel memory, and store butterfly group data and twiddle factors corresponding to the butterfly group data. The butterfly computation device perform computations of a butterfly group based on the butterfly group data outputted from the first selector and the corresponding twiddle factors outputted from one of the memories, and write a computation result back to the other two memories. The device can read butterfly group data and corresponding twiddle factors in parallel from the multi-granularity parallel memories with a specific R/W granularity. No memory conflict will occur in the read operation, and no additional process is required for sorting the read/written data.