FFT Memory Control Circuit Data Reordering for Hazard Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing FFT processing methods face inefficiencies due to memory hazards and the need for multiple clock cycles to change data storage locations, which hinder fast processing in Radix 2 and Radix 4 FFT operations.
Innovation Solution
A memory control method that adjusts data order to store computation results in specified locations, allowing for simultaneous data access and reduction of memory banks required, using a memory control circuit to manage data flow between operational circuits and memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data storage locations are changed using multiple clock cycles in conventional FFT processing, then data can be stored in different locations, but processing speed decreases and memory hazards occur
Solution Approach 1:
The memory control circuit pre-arranges data in the memory banks in an order that anticipates future processing needs. By organizing data beforehand in the correct sequence, the system eliminates the need for time-consuming data relocation operations during FFT processing, thereby resolving the contradiction between processing speed and time consumption for data location changes.
Solution Approach 2:
The memory control circuit acts as an intermediary between the memory banks and the FFT processing unit. It manages data flow and ordering independently, allowing the FFT processor to operate continuously without waiting for data repositioning. This mediator role eliminates memory hazards and prevents processing delays.
2Quantity of substance
If multiple memory banks are used to store data for FFT processing, then data storage capacity increases, but hardware size increases
Solution Approach 1:
Each memory bank is designed to handle multiple functions: storing input data, storing intermediate results, and storing output data. The memory banks can be dynamically allocated to different purposes depending on the processing stage. This multi-functionality allows the system to achieve the required data storage capacity using fewer memory banks, thereby reducing hardware complexity.
Solution Approach 2:
The system dynamically reuses memory bank contents across different processing stages. Data that has been processed in one stage is retained and reused in subsequent stages without requiring additional memory banks. This dynamic reuse of memory resources achieves the necessary storage capacity while minimizing the number of physical memory banks required.
3Productivity
If data is not stored in optimal locations, then memory access is simpler, but successive operations cannot be performed efficiently
Solution Approach 1:
The memory system is segmented into multiple banks, each capable of independent access. The memory control circuit segments the data flow management, directing different data streams to appropriate banks based on processing stage. This segmentation allows efficient successive operations on different data segments simultaneously, improving productivity while managing complexity through structured organization.
Solution Approach 2:
The memory control circuit changes the addressing parameters and data organization format based on the processing stage. By dynamically adjusting how data is arranged and addressed in memory, the system optimizes for successive operations without requiring complex hardware changes. This parameter-based control achieves efficiency while keeping the hardware structure relatively simple.
Data Source
AI summary
An FFT operational device includes memory banks, an FFT operational circuit, and an FFT memory control circuit. The memory banks can overwrite pieces of data to specified address locations simultaneously or read out the data from the locations simultaneously. The operational circuit receives operands read out from the banks simultaneously to perform an FFT operation processing on the operands to output operation results simultaneously, and repeats the FFT operation processing a predetermined number of times. The memory control circuit receives the operation results output from the operational circuit simultaneously, and changes the order of the data in such a way that the pieces of data required for the operational circuit in the successive operation processing will be provided simultaneously. The resultant data are overwritten to the memory banks. The operational device thereby performs FFT or IFFT processing on hardware, the storage capacity thus being reduced with operational speed increased.