Radix K FFT Memory Segmentation for Chip Area Reduction
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Solution Overview
Problem
The calculation of Fast Fourier Transform (FFT) is a resource-intensive operation in digital signal processing, consuming significant chip area and power, necessitating improvements to reduce resource consumption.
Innovation Solution
The implementation of a radix K decomposition of FFT, where N/K input data elements are written to K addressable memories and undergo N/K*logK passes, with parallel reading, permutation, radix K calculation, and writing of result data elements, optimizing memory access and reducing resource requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional FFT implementation is used, then accurate FFT calculations are achieved, but significant chip area and power consumption are required
Solution Approach 1:
The patent segments the FFT calculation into K independent stages, each processing N/K data elements simultaneously. This segmentation allows the use of K smaller memory units instead of one large memory bank, reducing overall chip area while maintaining calculation accuracy through the systematic decomposition of the transform into manageable segments.
Solution Approach 2:
The patent introduces a memory addressing dimension based on radix-K decomposition. By organizing data access through K different address spaces rather than a single linear memory bank, the system achieves efficient parallel access patterns that reduce the total memory area required while preserving FFT computational integrity.
2Reliability
If traditional FFT implementation is used, then accurate FFT calculations are achieved, but significant power consumption is required
Solution Approach 1:
The patent divides the FFT computation into K parallel segments that can be processed simultaneously. This segmentation enables more efficient data access patterns and reduces the total active circuit area at any given time, thereby lowering power consumption while maintaining calculation accuracy through the distributed computational approach.
Solution Approach 2:
The patent performs preliminary data organization and addressing setup before the main FFT computation. By pre-configuring the memory addressing sequences and data distribution patterns, the system minimizes runtime overhead and reduces the energy required for data management operations during the actual transform calculation.
3Area of stationary object
If K addressable memories are used with parallel reading, then resource consumption is reduced, but complex control arrangements are required
Solution Approach 1:
The patent implements dynamic memory addressing where the address patterns change systematically across the N/K*logK passes. The control arrangements adapt the addressing sequences based on the current pass number and data element requirements, enabling efficient parallel access to K memories while managing complexity through algorithmic control rather than static hardwired connections.
Data Source
AI summary
Various approaches for performing a fast-Fourier transform (FFT) of N input data elements using a radix K decomposition of the FFT are disclosed (K>=2, and N>=8). In one approach, N/K input data elements are written to respective ones of K addressable memories, and N/K*logK N passes are performed on the input data. Each pass includes reading K data elements in parallel from the K addressable memories using the respectively generated addresses, the K data elements being in a first order corresponding to the respective memories; permuting the first order of K data elements into a second order of K data elements; performing a radix K calculation on the second order of K data elements, resulting in corresponding result data elements in the second order; permuting the second order of K result data elements into the first order; and writing the K result data elements in parallel to the corresponding K addressable memories using the respective addresses.