Multi-Stage FFT Engine Data Normalization for Buffer Reduction

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Solution Overview

Problem

Modern wireless communication systems face challenges in reducing the size of FFT engine output buffers due to the large dynamic range of received OFDM signals, which necessitates significant memory usage and increases computational resources.

Innovation Solution

Implementing a series of stages in the FFT engine with butterflies and data normalization devices that scale output signals, allowing for bit-width reduction and smaller buffer sizes by normalizing the signals between stages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the FFT engine processes received OFDM signals without data normalization, then the dynamic range of the output signal is maintained, but the buffer size and computational resources increase significantly

Engineering Contradiction:
Improvedynamic range performanceVSAvoidbuffer size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The FFT processing is divided into multiple stages, with data normalization applied between stages. This segmentation allows the system to manage the dynamic range in increments rather than handling the full range in a single operation, reducing the buffer size required at each stage while maintaining overall dynamic range performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter of signal amplitude by applying data normalization (scaling) between FFT stages. This parameter change reduces the dynamic range of intermediate results, allowing for smaller buffer sizes and reduced computational resources while the final stage restores the original dynamic range to maintain performance.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If the FFT engine uses multiple stages with data normalization, then the buffer size and computational resources are reduced, but the device complexity increases

Engineering Contradiction:
Improvebuffer sizeVSAvoidFFT engine structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

By dividing the FFT engine into multiple stages with normalization operations between them, the patent reduces the buffer size required at each stage. The segmentation creates manageable intermediate results that require less memory, offsetting the increased structural complexity with reduced resource requirements.

Inventive Principle:
Principle #1Segmentation

3Reliability

If the FFT engine processes signals with large dynamic range, then the signal quality is maintained, but the computational operations increase

Engineering Contradiction:
Improvesignal qualityVSAvoidcomputational efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies parameter changes by normalizing the signal amplitude between FFT stages. This reduces the dynamic range of intermediate computational operations, decreasing the number of computational operations required while maintaining signal quality through proper scaling at each stage and restoration at the final stage.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8218426B2Multiple stage fourier transform apparatus, processes, and articles of manufacture
Publication Date: 2012.07.10 QUALCOMM INC
  • US8218426B2 patent drawing
  • US8218426B2 patent drawing
  • US8218426B2 patent drawing

AI summary

In embodiments, a fast Fourier transform (FFT) engine includes a series of stages, each stage containing a butterfly and a data normalization device configured to scale output of the stage's butterfly. The scaling factors are adjusted, for example, periodically or on as-needed basis, so that the dynamic range of the butterflies and the buffers is increased for a given bit-width, or the bit-width of these devices is decreased for the same dynamic range. Additionally, bit-width of other buffer(s) is decreased because of the scaling of the data.