FFT Operating Apparatus with Offset Address Generation
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Solution Overview
Problem
Conventional digital signal processors face challenges in reducing the number of operation cycles required for Fast Fourier Transform (FFT) operations, particularly in programmable processors, due to complex hardware configurations and limited parallel processing capabilities, leading to inefficiencies in butterfly operations and data addressing.
Innovation Solution
A radix-2 complex FFT operation method is implemented in a programmable processor, which generates a start signal, calculates and stores offset addresses for butterfly input/output data, and uses two multiplier-accumulators to perform butterfly operations efficiently, minimizing additional operation cycles through optimized data processing and address calculation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If radix-2 DIT FFT is used with simpler butterfly structure, then device complexity is reduced, but the number of stages increases leading to more operation cycles
Solution Approach 1:
The patent segments the FFT operation into distinct functional modules: address generation unit, data processing unit with butterfly operation circuits, and result storage unit. This segmentation allows parallel execution of address calculation and data processing, reducing the total operation cycles while maintaining the simple radix-2 butterfly structure.
Solution Approach 2:
The address generation unit pre-calculates and prepares the addresses for butterfly operations before the actual data processing occurs. This preliminary action enables the data processing unit to immediately access required data without waiting for address calculation, thereby reducing operation cycles.
2Productivity
If radix-4 DIT FFT is used for high speed processing, then productivity is improved, but device complexity increases with more multipliers
Solution Approach 1:
The patent merges multiple butterfly operations into a single clock cycle by combining multiple multiplier-accumulators in parallel. This allows the processing unit to complete what would traditionally require multiple sequential stages in a single cycle, achieving high-speed processing without increasing individual butterfly complexity.
Solution Approach 2:
The patent transitions from sequential time-based processing to parallel spatial processing by implementing multiple butterfly operation circuits that operate simultaneously. This dimensional change from time-sequential to space-parallel execution achieves radix-4-like processing speed while maintaining simpler individual butterfly structures.
3Area of stationary object
If single multiplier-accumulator is used, then area is reduced, but productivity decreases with more operation cycles
Solution Approach 1:
The patent implements a dual multiplier-accumulator architecture where both units operate continuously and simultaneously on different data pairs. This continuous parallel operation doubles the processing throughput compared to a single unit, achieving high productivity while keeping the area increase minimal by using identical circuit blocks.
Data Source
AI summary
A fast Fourier transform (FFT) operating apparatus and a method thereof carries out an FFT operation in a programmable processor chip. A program controller generates an FFT start signal and controls a programmable processor, and a program memory stores an application of the programmable processor. An FFT address generator removes the looping instruction used for the FFT and a cycle for an address generator, and generates an offset address of a butterfly input data and an operation end signal. An address generator calculates an address of a data memory using the offset address generated in the FFT address generator and a data memory stores data. A data processor carries out an arithmetic and logic operation using the data stored in the data memory and a flag register generates an FFT operation signal.