FFT Signal Normalization Using Partial Sign-Magnitude Encoding
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Solution Overview
Problem
Existing FFT/IFFT processing methods require large circuit scales and high power dissipation due to the use of two's complement representation for signals near zero, which leads to high bit-wise operation rates, and the conversion between two's complement and sign magnitude representations increases circuit scale and power dissipation.
Innovation Solution
A signal processing apparatus and method that uses a partial sign magnitude representation for negative values, combined with block floating point normalization, to reduce circuit scale and power dissipation by minimizing bit-wise operation rates and eliminating the need for add-one processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two's complement representation is used for signal data, then addition and subtraction can be performed using the same circuit, but the bit-wise operation rate increases for signals near zero, leading to high power dissipation
Solution Approach 1:
The patent changes the representation format parameter from two's complement to a modified format where negative values have inverted bits. This parameter change reduces the bit-wise operation rate for signals near zero, thereby reducing power dissipation while maintaining circuit compatibility
Solution Approach 2:
The patent applies bit inversion selectively to specific bit positions (D−N−1 bits between MSB and N consecutive lower bits) rather than uniformly across all bits. This local modification optimizes power dissipation for critical signal ranges while preserving the benefits of two's complement representation
2Use of energy by moving object
If sign magnitude representation is used to reduce bit-wise operation rate, then power dissipation decreases, but conversion between two's complement and sign magnitude increases circuit scale and power dissipation
Solution Approach 1:
The patent applies partial bit inversion rather than complete sign magnitude conversion. By inverting only (D−N−1) specific bits instead of all bits, it achieves power dissipation reduction with minimal circuit complexity increase, avoiding full conversion infrastructure
Solution Approach 2:
The patent segments the bit representation into distinct regions: MSB (sign bit), (D−N−1) inverted bits, and N consecutive lower bits. This segmentation allows selective processing and storage without requiring complete format conversion circuits
3Device complexity
If FFT processing is implemented by repeatedly utilizing a partial processing circuit, then circuit scale is reduced, but processing time increases due to sequential operation
Solution Approach 1:
The patent enables dynamic operation mode selection for the FFT circuit, allowing it to function as a pipeline processor for parallel processing or as a sequential processor for power-saving operation. This dynamic adaptability optimizes the balance between processing speed and power consumption based on application requirements
Data Source
AI summary
A signal processing apparatus includes a storage processing part to perform processing on data represented in a second representation format, wherein the second representation format, while for a non-negative value identical to two's complement representation, for a negative value, has a representation format where (D−N−1) bits of the data of D-bits in the two's complement representation are bit-wise inverted, the (D−N−1) bits located between MSB and N consecutive lower bits including LSB, the storage processing part including a normalization circuit with a maximum exponent calculation circuit and a shift circuit to normalize a plurality of pieces of data represented in the second representation format for each block.