FFT Computing Apparatus with Concurrent Power Computation
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Solution Overview
Problem
Existing FFT computing circuits face issues with increased circuit area overhead and processing delay when computing received signal power, particularly in digital baseband processing for OFDM systems, due to the need for dedicated arithmetic circuits and DSP processing.
Innovation Solution
An FFT computing apparatus with a computation-unit switching detection unit that identifies timing when complex multiplication is not required in butterfly computations, allowing for simultaneous power computation using a complex-multiplication power-computation unit, thereby reducing circuit area overhead and processing delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dedicated arithmetic circuit is used for power computation after FFT processing, then power computation accuracy is improved, but circuit area overhead increases
Solution Approach 1:
The complex multiplier unit in the FFT computation circuit is designed to perform multiple functions: complex multiplication during FFT processing and power computation when complex multiplication is not required. This multi-functional design eliminates the need for a separate dedicated power computation circuit, thereby reducing circuit area overhead while maintaining power computation accuracy
Solution Approach 2:
The power computation function is merged with the existing FFT computation circuit by utilizing the complex multiplier unit. The control unit coordinates both FFT and power computation operations through a single integrated circuit structure, combining what were previously separate functions into one unified system
2Adaptability or versatility
If a DSP processor is used for power computation after FFT processing, then processing flexibility is improved, but processing delay increases
Solution Approach 1:
The control unit enables continuous operation by identifying and utilizing time periods when the complex multiplier is not required for FFT computation to perform power computation. This ensures that the useful action of computation continues without idle periods, reducing overall processing delay while maintaining the flexibility of DSP processing
Solution Approach 2:
The control unit提前 identifies timing when complex multiplication is not required and prepares to execute power computation during these intervals. By planning and executing power computation in advance during available time slots, the system reduces overall processing delay while maintaining flexibility
3Measurement precision
If power computation is performed after FFT processing using separate circuits, then computation accuracy is improved, but device complexity increases
Solution Approach 1:
The complex multiplier unit is designed to serve dual purposes: performing complex multiplication during FFT stages and executing power computation when multiplication is not needed. This universal design maintains computation accuracy through proper mathematical operations while reducing device complexity by eliminating redundant dedicated circuits
Solution Approach 2:
The FFT computation circuit serves its own power computation needs by utilizing its existing complex multiplier unit. The system is self-sufficient, using its own computational resources to perform power computation without requiring external dedicated circuits, thereby reducing overall device complexity
Data Source
AI summary
In an FFT computing apparatus, a computation-unit switching detection unit detects timing at which a complex multiplication is not being carried out in said butterfly computation of FFT computation, and a complex-multiplication power-computation unit switches computation between complex multiplication and power computation, based on a detection result by said computation-unit switching detection unit. The complex-multiplication power-computation unit performs power computation at timing at which complex multiplication is not carried out in said butterfly computation of FFT computation.