Non-power-of-2 FFT Processing Circuit with Customized Instructions
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Solution Overview
Problem
Implementing Fast Fourier Transform (FFT) algorithms with lengths that are not a power-of-2 poses challenges in Digital Radio Mondiale (DRM) applications, as existing solutions are costly and inefficient, particularly for lengths like 352 and 224, which are not supported by standard libraries.
Innovation Solution
A method for implementing non-power-of-2 FFTs using a processing circuit with parallel processing units, employing customized instructions to perform FFT operations by decomposing the transform into smaller co-prime length FFTs and optimizing data processing to bypass unnecessary processing elements, thereby supporting efficient computation on SIMD vector processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard FFT libraries are used for power-of-2 lengths, then implementation is easy and efficient, but non-power-of-2 FFT lengths (like 352 and 224) cannot be supported
Solution Approach 1:
The patent segments non-power-of-2 FFT computations into multiple smaller power-of-2 FFT operations. For example, a 352-point FFT is decomposed into smaller FFTs of lengths that are powers of 2, allowing the use of efficient power-of-2 algorithms while supporting non-power-of-2 overall lengths. This segmentation enables versatility in supported FFT lengths without sacrificing implementation efficiency.
2Adaptability or versatility
If non-power-of-2 FFTs are implemented using decomposition methods, then supported FFT lengths increase, but computational complexity and processing overhead increase
Solution Approach 1:
The patent changes the parameter of FFT length support to include non-power-of-2 values by modifying the decomposition strategy. Instead of requiring direct power-of-2 lengths, the system transforms the problem into multiple power-of-2 sub-problems with adjusted parameters, thereby expanding adaptability while managing computational complexity through optimized decomposition algorithms.
3Productivity
If customized instructions are used for non-power-of-2 FFTs, then computational efficiency improves, but hardware complexity increases
Solution Approach 1:
The patent uses copying by replicating power-of-2 FFT processing units to handle non-power-of-2 FFT lengths. Instead of designing completely new hardware for each non-power-of-2 length, the system copies and reconfigures existing power-of-2 FFT units, achieving computational efficiency for specialized operations while minimizing hardware complexity through reuse of proven designs.
4Reliability
If DRM-specific FFT lengths (352, 224) are supported, then application performance improves, but memory usage and processing resources increase
Solution Approach 1:
The patent applies dynamics by making the FFT processing configuration adaptable to different DRM-specific lengths (352, 224) through dynamic decomposition into power-of-2 segments. This allows the system to optimize memory usage and processing resources for each specific DRM mode by dynamically selecting appropriate decomposition strategies, rather than allocating resources for all possible FFT lengths simultaneously.
Data Source
AI summary
An embedded system is described. The embedded system includes a processing circuit comprising ‘Q’ processing units that can be operated in parallel. A memory is operably coupled to the processing circuit and includes at least input data. The processing circuit is configured to support an implementation of a non-power-of-2 fast Fourier transform of length N using a multiplication of at least two smaller FFTs of a respective first length N1 and second length N2, where N1 and N2 are whole numbers. The processing circuit is further configured to employ a customized instruction configured to perform an FFT operation of length less than ‘Q’ using a first of the at least two smaller FFTs.