FFT Processor Architecture with Shared ROM for Silicon Area Reduction
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Solution Overview
Problem
Modern wideband communication systems and radar systems that employ fast Fourier transform (FFT) processors face challenges with silicon area occupation and memory access conflicts due to the large number of twiddle factors required for long FFT algorithms, especially in parallel computation scenarios.
Innovation Solution
A parallel memory-based FFT processor architecture that includes multiple processing units, data memory banks, and coefficient memory banks for efficient twiddle factor storage and retrieval, utilizing a burst-based data processing scheme and a ROM address generator to avoid memory access conflicts and reduce silicon area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a plurality of processing elements and ROM memories are used for parallel FFT computation, then processing throughput is improved, but silicon area occupation increases significantly
Solution Approach 1:
Multiple processing elements share a single ROM memory resource instead of each having dedicated ROM. The ROM is time-multiplexed among processing elements through coordinated address generation, reducing total ROM quantity while maintaining parallel processing capability
Solution Approach 2:
The single ROM memory serves multiple processing elements simultaneously by generating different address sequences for different PEs. The same physical ROM resource performs the twiddle factor storage function for multiple processing units through universal address mapping
2Reliability
If multiple dedicated ROM memories are provided for each processing element, then memory access conflicts are avoided, but device complexity increases
Solution Approach 1:
An address generator circuit acts as an intermediary between processing elements and the shared ROM memory. This mediator generates distinct address sequences for each processing element, enabling conflict-free access to the shared ROM resource without requiring dedicated ROM for each PE
3Measurement precision
If a large number of twiddle factors are stored in ROM memories, then FFT computation accuracy is maintained, but silicon area occupation increases
Solution Approach 1:
The large set of twiddle factors is segmented into smaller subsets that are accessed by different processing elements at different times. Each processing element receives only the specific twiddle factors it needs for its current computation stage, reducing total ROM storage requirements while maintaining computational accuracy
Data Source
AI summary
An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.