FFT Hardware Architecture Using Radix-p Engines for Arbitrary Sizes
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Solution Overview
Problem
Existing hardware architectures for Fast Fourier Transform (FFT) calculations are inefficient in terms of memory and multiplier usage, particularly for non-power of 2 FFT sizes, and fail to optimize for varying application requirements such as memory or performance needs.
Innovation Solution
A novel hardware architecture that implements FFT using a multi-stage iterative structure with radix-p engines, allowing for flexible resource allocation and efficient memory usage by decomposing the DFT into smaller factors and using shadow memory blocks, enabling efficient computation for arbitrary FFT sizes and optimizing memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional hardware architectures for FFT are used, then computation speed can be achieved, but memory and multiplier usage become inefficient
Solution Approach 1:
The FFT computation is divided into multiple stages, with each stage processing a portion of the data. The architecture uses a multi-stage iterative structure where each stage performs partial computations and passes results to the next stage, reducing the memory and computational resources required at any single point in time.
Solution Approach 2:
The hardware architecture is designed to be reconfigurable and adaptive, allowing it to optimize resource allocation based on the specific FFT size and application requirements. The system can dynamically adjust its operation mode to balance between throughput and resource utilization efficiency.
2Productivity
If hardware architectures are optimized for power of 2 FFT sizes, then computation efficiency improves, but flexibility for arbitrary FFT sizes deteriorates
Solution Approach 1:
The hardware architecture is designed to handle arbitrary FFT sizes rather than being limited to power of 2 sizes. The multi-stage iterative structure with radix-p engines can be configured to process different FFT lengths, making the system universal and adaptable to various application requirements without sacrificing computational efficiency.
3Productivity
If high-performance hardware architectures are implemented, then throughput and latency requirements are met, but resource utilization in FPGA and ASIC deteriorates
Solution Approach 1:
The architecture implements a pipelined structure where data flows continuously through multiple stages of computation. Each stage processes data as it becomes available, eliminating idle time and ensuring continuous useful action throughout the system, thereby achieving high throughput without requiring excessive resources.
Solution Approach 2:
By segmenting the FFT computation into multiple stages that can operate in parallel or pipeline fashion, the architecture achieves high throughput while distributing resource requirements across time and space, improving overall resource utilization efficiency in FPGA and ASIC implementations.
Data Source
AI summary
Improved devices and methods for performing Fast Fourier Transforms.