FFT Sample Reorder Circuit for Dynamic Channelizer
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Solution Overview
Problem
Existing channelizer architectures are inefficient due to layout-based and performance-based issues such as duplicative circuitry, over-reliance on large registers, and underutilized mathematical operators, making them unsuitable for applications requiring dynamic reconfiguration in constrained environments like airborne or spaceborne platforms.
Innovation Solution
A dynamically reconfigurable 2X oversampled channelizer using pipelined stages, polyphase filters, two-phase reorder circuits, FFT circuits, and two-phase merge circuits, allowing for in-field modification of channelization parameters like filter coefficients, number of frequency bins, and filter taps, suitable for FPGAs, CPLDs, and ASICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing channelizer architectures are used, then channelization can be performed, but resource duplication and inefficiency occur due to layout-based issues and duplicative circuitry
Solution Approach 1:
The patent merges multiple channelizer functions into a unified architecture that processes multiple frequency bins simultaneously. The polyphase filter bank and FFT circuit are integrated to share computational resources, eliminating duplicative circuitry while maintaining the ability to perform channelization across multiple frequency bins. This consolidation reduces hardware resources and improves manufacturing efficiency.
2Productivity
If existing channelizer architectures are used, then channelization can be performed, but performance is degraded due to over-reliance on large registers
Solution Approach 1:
The patent replaces the traditional mechanical approach of using large register-based buffers with a streaming processing architecture. Data flows continuously through pipelined stages including polyphase filtering, FFT computation, and frequency bin output without requiring large stationary memory structures. This substitution maintains high throughput while dramatically reducing the quantity of register resources required.
3Adaptability or versatility
If existing channelizer architectures are used, then channelization can be performed, but adaptability is limited due to underutilized mathematical operators and fixed structure
Solution Approach 1:
The patent implements a dynamically reconfigurable architecture where the number of frequency bins, filter coefficients, and FFT size can be adjusted in real-time. The underlying mathematical operators (polyphase filtering, FFT computation) are fully utilized and can be reconfigured through software control without hardware changes. This dynamic capability allows the system to adapt to different signal processing requirements while maintaining efficient use of mathematical operations.
Data Source
AI summary
Techniques are provided for a fast Fourier transform (FFT) sample reorder circuit for a dynamically reconfigurable oversampled channelizer. An FFT sample reorder circuit implementing the techniques according to an embodiment includes a plurality of dual port memory circuits. The circuit also includes a first crossbar circuit configured to route input data samples to write ports of the plurality of dual port memory circuits. The circuit further includes a second crossbar circuit configured to route reordered output data samples from read ports of the plurality of dual port memory circuits to a multi-stage FFT circuit. The circuit further includes a controller circuit configured to control the routing of the input data samples and the routing of the reordered output data samples based on a selection of a stage of the multi-stage FFT circuit.