In-Place FFT and Multi-Pass Reordering for Normally Ordered Fourier Coefficients

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Solution Overview

Problem

Current radar signal processing techniques face challenges in efficiently producing normally ordered Fourier coefficients and optimizing compute resource usage while minimizing memory requirements and data transfer activity, particularly in streaming, real-time, embedded digital systems.

Innovation Solution

The fusion of in-place fast Fourier transform (FFT) and multi-pass reordering algorithms for bit reversal, specifically combining decimation-in-time (DIT) FFT with vector reordering techniques, to produce normally ordered Fourier coefficients and optimize computational resource usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If standard in-place FFT is used, then computational efficiency is improved, but normally ordered Fourier coefficients cannot be produced without additional reordering operations

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidreordering operations
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the in-place FFT computation with multi-pass reordering algorithms into a unified approach. The reordering operations are integrated into the FFT computation stages, allowing both the Fourier transform and bit reversal to occur simultaneously without requiring separate sequential operations, thus resolving the contradiction between computational efficiency and operational complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent applies preliminary reordering actions during the FFT computation process itself. By incorporating reordering operations into the FFT stages (particularly in the decimation-in-time approach), the system performs bit reversal before the final output is needed, eliminating the need for post-computation reordering and maintaining computational efficiency while producing normally ordered coefficients

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If multi-pass reordering algorithms are added to produce normally ordered coefficients, then output correctness is improved, but memory requirements and data transfer activity increase

Engineering Contradiction:
Improveoutput correctnessVSAvoidmemory requirements
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent combines the reordering operations with the FFT computation in-place, eliminating the need for separate buffer memory allocations. The multi-pass reordering is performed using the same memory space as the FFT computation, reducing overall memory requirements while still producing correctly ordered output coefficients

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent maintains continuous useful action by performing reordering operations during the FFT computation process rather than as separate discrete steps. The reordering is integrated into the computation stages, allowing memory to be reused for both transformation and reordering operations, thereby reducing total memory requirements while ensuring output correctness

Inventive Principle:
Principle #20Continuity of useful action

3Speed

If conventional FFT processing is used, then computational speed is maintained, but data transfer activity between memory and processing units increases

Engineering Contradiction:
Improvecomputational speedVSAvoiddata transfer activity
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent performs reordering actions preliminarily during the FFT computation process. By incorporating bit reversal operations into the FFT stages themselves, the system eliminates the need for subsequent data transfer and reordering operations, reducing overall data transfer activity while maintaining computational speed through integrated processing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuous useful computation by integrating reordering operations into the FFT processing pipeline. This eliminates idle data transfer phases and ensures that memory bandwidth is continuously utilized for productive computation rather than for moving data between memory and processing units, thereby reducing energy loss from data transfer

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11378650B1Radar signal processing techniques and radar system
Publication Date: 2022.07.05 LAUGINIGER FRANK
  • US11378650B1 patent drawing
  • US11378650B1 patent drawing
  • US11378650B1 patent drawing

AI summary

Radar signal processing techniques and a radar system are disclosed. The disclosed techniques include producing normally ordered Fourier coefficients via fusion of in-place fast Fourier transform (FFT) and multi-pass reordering algorithms for bit reversal. The fusion of an in-place, decimation-in-time (DIT) FFT with a collection of vector reordering algorithms results in a new group of algorithms capable of producing normally ordered Fourier coefficients. Techniques disclosed herein are utilizable, for example, in simultaneous FFT butterfly computations and self-sorting or reordering bit reversal. Techniques disclosed herein are utilizable, for example, in the context of compute resource usage for a given compute platform.