Pipelined FFT Shuffler for 60 GHz Multipath Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current wireless communication systems in the 60 GHz frequency band face challenges with multipath reflection, Inter Symbol Interference (ISI), and channel capacity, which are not efficiently addressed by existing technologies, particularly in terms of power efficiency and latency in single-carrier systems.
Innovation Solution
The implementation of a pipelined Fast Fourier Transform (FFT) architecture that partitions 9-bit addresses into triplets, permutes them to generate different permutations for memory access, and uses barrel shifters to efficiently shift symbols between data lanes, allowing for reduced latency and power consumption in frequency domain equalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fully-pipelined FFT architecture is implemented, then processing speed and throughput are improved, but device complexity and power consumption increase
Solution Approach 1:
The FFT processing is divided into multiple pipeline stages, with each stage handling a specific portion of the computation. The architecture segments the input data into different lanes (Lane 0, Lane 1, Lane 2, Lane 3) that are processed independently through the pipeline, allowing concurrent execution of multiple operations and improving overall throughput without requiring a single complex processing unit
Solution Approach 2:
The pipelined FFT architecture implements nested structures where butterfly operations are organized within stages, and stages are nested within the overall pipeline. The memory structure uses nested addressing schemes with base addresses and offsets, creating a hierarchical organization that manages complexity while maintaining high processing speed
2Productivity
If address permutation and barrel shifter operations are implemented, then memory access efficiency is improved, but device complexity increases
Solution Approach 1:
Address permutation is pre-computed and stored in lookup tables before the actual FFT processing begins. The base addresses and offsets are calculated in advance, allowing the pipeline to directly access memory locations without real-time computation overhead, thus improving memory access efficiency while keeping the runtime device complexity manageable
Solution Approach 2:
The barrel shifter acts as an intermediary component that efficiently handles data lane switching and symbol repositioning. Instead of implementing complex routing logic throughout the entire system, the barrel shifter provides a dedicated, optimized component for address manipulation and data reordering, simplifying the overall device architecture while maintaining high memory access efficiency
Data Source
AI summary
A plurality of three bit units (called triplets) are permuted by a shuffler to shuffle the positions of the triplets into different patterns which are used to specific the read/write operation of a memory. For example, the least significant triplet in a conventional counter can be placed in the most significant position of a permuted three triplet pattern. The count of this permuted counter triplet generates addresses that jump 64 positions each clock cycle. These permutations can then be used to generate read and write control information to read from/write to memory banks conducive for efficient Radix-8 Butterfly operation. In addition, one or more triplets can also determine if a barrel shifter or right circular shift is required to shift data from one data lane to a second data lane. The triplets allow efficient FFT operation in a pipelined structure.