FFT Processor Architecture Using Vector and Matrix Operation Circuits
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Solution Overview
Problem
Existing methods for performing Fast Fourier Transform (FFT) using scalar and/or vector operation circuits are inefficient.
Innovation Solution
Implementing FFT calculations using a processor with both a vector operation circuit and a matrix operation circuit, where rotation factor calculation is performed by the vector operation circuit and DFT calculation is performed by the matrix operation circuit, optimizing the decomposition and execution of FFT stages to improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FFT calculation is implemented using only scalar operation circuit or vector operation circuit, then device complexity is reduced, but calculation efficiency deteriorates
Solution Approach 1:
The processor is segmented into two specialized operation circuits: a vector operation circuit for rotation factor calculation and a matrix operation circuit for DFT calculation. This segmentation allows each circuit to be optimized for its specific function, improving overall FFT calculation efficiency while maintaining manageable device complexity through functional separation.
2Loss of time
If rotation factor calculation and DFT calculation are performed using the same operation circuit, then device complexity is reduced, but calculation time increases
Solution Approach 1:
The FFT calculation process is segmented into two distinct calculation tasks performed by separate circuits: rotation factor calculation by the vector operation circuit and DFT calculation by the matrix operation circuit. This segmentation enables parallel execution of these tasks, reducing total calculation time while the specialized structure of each circuit keeps individual complexity low.
Solution Approach 2:
The invention transitions from a single-dimensional operation circuit that handles all calculations sequentially to a two-dimensional architecture where vector operations and matrix operations are performed in parallel on different dimensions. This dimensional expansion allows simultaneous execution of rotation factor calculation and DFT calculation, reducing overall calculation time.
3Measurement precision
If matrix size in DFT calculation is increased, then calculation precision is improved, but memory access discontinuity increases
Solution Approach 1:
The matrix operation circuit is designed with local quality optimization where data is accessed and processed in localized patterns that match the mathematical structure of DFT calculations. The circuit performs complex matrix multiplication by systematically accessing real and imaginary parts of input data and DFT matrix elements in a pattern that maintains precision while improving access continuity through localized memory operations.
Data Source
AI summary
Embodiments disclosed in this application pertain to the field of computer technologies, and in particular, to a method for performing FFT, a processor, and a computing device. The method includes: A processor responds to an execution request of fast Fourier transform FFT calculation of an application, and decomposes the FFT calculation into a plurality of calculation stages. The processor sequentially executes the plurality of calculation stages, where when a target calculation stage is executed, a vector operation circuit performs rotation factor calculation, and a matrix operation circuit performs DFT calculation. After the execution of the plurality of calculation stages is completed, the processor determines an execution result of the FFT calculation based on an execution result of a last calculation stage, and returns the execution result to the application. vector operation circuit matrix operation circuit