FHE Bootstrapping Accelerator Using Parallel NTT and Gadget Decomposition
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Solution Overview
Problem
Existing Fully Homomorphic Encryption (FHE) systems face challenges in efficiently reducing noise in operated ciphertexts, particularly in the TFHE algorithm, which requires frequent bootstrapping operations, leading to significant overhead and slowing down processing.
Innovation Solution
An accelerator device is introduced that includes various converters and multipliers to perform parallel operations such as NTT, INTT, CRT, and ICRT, along with gadget decomposition, to accelerate the bootstrapping process of FHE, specifically for TFHE, by utilizing hardware accelerators to handle tasks like blind rotate, sample extraction, and key exchange.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bootstrapping operations are performed frequently to reduce noise in operated ciphertexts, then the quality of ciphertext is improved, but the processing time and computational overhead increase significantly
Solution Approach 1:
The accelerator device divides the bootstrapping process into multiple independent parallel operations including NTT conversion, multiplication, INTT conversion, and CRT conversion. Each operation is handled by dedicated hardware modules that can process different parts of the ciphertext simultaneously, reducing the overall time required for bootstrapping while maintaining ciphertext quality.
Solution Approach 2:
The patent transitions from sequential software-based bootstrapping to parallel hardware-based processing by introducing multiple conversion modules (NTT, INTT, CRT) that operate simultaneously on different data streams. This dimensional shift from time-sequential to space-parallel processing dramatically reduces the time overhead of frequent bootstrapping operations.
2Productivity
If hardware accelerators are introduced to speed up bootstrapping operations, then processing speed is improved, but device complexity increases
Solution Approach 1:
The accelerator device employs universal hardware modules such as NTT converters and multiplication units that can handle multiple types of cryptographic operations. These modules are designed to process different ciphertext formats and cryptographic algorithms through the same hardware architecture, reducing overall device complexity while maintaining high processing speeds.
Solution Approach 2:
The patent uses multiple instances of identical conversion modules (NTT, INTT, CRT) that are replicated to handle parallel operations. Instead of designing complex single-purpose hardware for each operation, the system copies and deploys simpler modular units that can be instantiated multiple times, reducing the complexity of individual components while achieving high throughput through parallelization.
Data Source
AI summary
Disclosed is an accelerator device, which includes a first NTT converter that performs an NTT operation on a first ciphertext of a first type to generate a first internal signal, a test polynomial generator that generates a test polynomial, a second NTT converter that performs the NTT operation on the test polynomial to generate a second internal signal, a first multiplier that performs a multiplication on the first internal signal and the second internal signal to generate a third internal signal, a first INTT converter that performs an INTT operation on the third internal signal to generate a fourth internal signal, a gadget decomposer that performs a gadget decomposition on the fourth internal signal to generate a fifth internal signal, and a third NTT converter that performs the NTT operation on the fifth internal signal to generate a sixth internal signal.