FHE Chip Multistage Interconnection Network for Ciphertext Operations
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Solution Overview
Problem
Existing FHE chips face challenges in efficiently performing ciphertext operations due to high computational complexity and resource-intensive NoCs, which lead to performance bottlenecks and increased chip resource consumption.
Innovation Solution
The FHE chip incorporates a multistage interconnection network (MIN) and n processor elements (PEs) to execute operation tasks in parallel, utilizing point-to-point data transmission for switching data, thereby reducing the need for extensive NoC resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a traditional NoC is used for data transmission between PEs, then bandwidth and coverage are sufficient, but implementation area and resource consumption increase significantly
Solution Approach 1:
The patent segments the data transmission function by separating switching data transmission from general data transmission. The MIN is specifically dedicated to switching data transmission between PEs, while traditional NoC handles other communication needs. This segmentation allows each subsystem to be optimized for its specific purpose, reducing overall resource consumption.
Solution Approach 2:
The MIN serves multiple functions within the FHE chip: it enables point-to-point transmission of switching data between PEs, supports the parallel execution of ciphertext operations, and integrates with the existing NoC architecture. This multi-functionality reduces the need for separate dedicated transmission paths.
2Productivity
If more NoC resources are allocated for ciphertext operations, then computational performance improves, but chip resource consumption increases
Solution Approach 1:
The patent applies local quality by creating a specialized MIN with point-to-point transmission capabilities specifically for switching data between PEs during ciphertext operations. This localized optimization provides high-speed transmission exactly where needed without upgrading the entire NoC infrastructure, thus improving computational performance while controlling resource consumption.
3Loss of time
If point-to-point transmission is implemented for switching data, then access delay is reduced, but implementation complexity increases
Solution Approach 1:
The MIN is nested within the existing FHE chip architecture, integrating point-to-point transmission capabilities into the established PE structure and NoC framework. This nesting approach allows the sophisticated point-to-point transmission mechanism to be implemented without completely redesigning the chip architecture, thereby reducing implementation complexity while achieving reduced access delay.
Data Source
AI summary
Embodiments of this specification provide an FHE chip and a computing device. The FHE chip includes a MIN and n PEs, and n is an integer greater than 1. The n PEs are configured to execute n operation tasks that belong to a ciphertext operation in parallel in a process of performing the ciphertext operation on target ciphertext by the FHE chip, where the target ciphertext is obtained by processing raw data based on an FHE algorithm. The MIN is configured to support a first PE in transmitting switching data to a second PE, where the switching data belongs to an operation result generated by the first PE by executing the operation task, and the first PE and the second PE belong to the n PEs.