Configurable FHE Hardware Architecture for Parallel FFT Routing
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Solution Overview
Problem
Building a parallel hardware architecture capable of executing algorithmic operations like matrix-multiplication and butterfly-like algorithms, such as Fast Fourier Transform (FFT), is prohibitively expensive due to high cost overheads in implementing parallel computing engines and interconnecting routing circuitry.
Innovation Solution
A general-purpose hardware architecture with a register file, computing engines, and routing circuitry that dynamically adjusts parallelism and register scoping, using multiplexers and combinatorial logic to reduce overhead costs and increase flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If highly parallel computing engines and interconnecting routing circuitry are implemented to execute algorithmic operations like matrix-multiplication and FFT, then computational parallelism and processing speed are improved, but cost overhead and device complexity increase prohibitively
Solution Approach 1:
The patent implements dynamic configurability in the hardware architecture, allowing the system to adjust the degree of parallelism and routing topology based on computational requirements. Computing engines can be dynamically configured to operate in highly parallel mode when needed, while routing circuitry adapts its complexity to match actual data flow requirements, avoiding permanent over-provisioning of resources.
Solution Approach 2:
The hardware architecture is designed with universal computing engines and routing circuitry that can perform multiple algorithmic operations including matrix-multiplication, FFT, and other butterfly-like algorithms. This multi-functionality reduces the need for dedicated specialized hardware for each algorithm, thereby reducing overall device complexity while maintaining high computational parallelism across different workloads.
2Speed
If full parallelism is implemented in hardware architecture for executing algorithmic operations, then processing speed is improved, but cost overhead increases prohibitively
Solution Approach 1:
The patent implements partial parallelism where the degree of parallel execution is adjusted to match computational requirements. Rather than implementing full parallelism across all computing engines simultaneously, the system activates only the necessary number of parallel engines needed for each specific algorithmic operation, reducing hardware complexity while maintaining adequate processing speed.
Solution Approach 2:
The hardware architecture segments computing engines and routing circuitry into modular units that can be independently configured and activated. This segmentation allows the system to implement parallelism in a controlled, incremental manner rather than requiring all components to operate in full parallelism simultaneously, thereby reducing overall hardware complexity while preserving processing speed where needed.
Data Source
AI summary
An apparatus including a computer architecture is provided. The computer architecture includes: a register file; computing engines; and routing circuitry. The apparatus is configured to determine a target configuration associated with one or more computing engines and one or more register banks of the register file or a partition of the register file, based on a target parallelism and a target processing scope for processing data stored at the one or more register banks. The apparatus is configured to couple the one or more computing engines to the one or more register banks, using the routing circuitry, based on the target configuration. The apparatus is configured to perform, by the one or more computing engines and based on the coupling and the target configuration, one or more computing operations on data stored at one or more respective registers of the one or more register banks.