FHE Processing Unit Memory Organization for Butterfly Transform
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Solution Overview
Problem
Lattice-based cryptography systems, particularly in fully homomorphic encryption (FHE), face significant computation overhead due to large polynomial multiplication tasks, which are essential for achieving desired security levels and multiplicative depth, leading to slow processing and high resource consumption in combinational logic.
Innovation Solution
The proposed solution involves a FHE processing unit with a data memory, twiddle factor memory, and Butterfly (BF) cores, optimized for efficient Butterfly Transform operations, allowing multiple BF cores to perform operations in consecutive clock cycles without memory conflicts, and a memory organization layout for storing twiddle factor values to facilitate high throughput without increasing combinational logic resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If larger parallel computing is used to improve processing speed, then throughput is improved, but the consumption of combinational logic resource is significantly increased
Solution Approach 1:
The patent divides the FHE processing unit into multiple independent Butterfly (BF) cores, each capable of performing transform operations autonomously. This segmentation allows parallel processing of polynomial transformations without requiring a monolithic increase in combinational logic, as each BF core is a modular unit that can be instantiated independently.
Solution Approach 2:
The patent introduces a temporal dimension to the data flow by using pipeline registers and clock cycle sequencing. Instead of requiring all data to be available simultaneously in a single combinational logic layer, the system stages data through multiple clock cycles, reducing the combinational logic depth while maintaining parallel throughput capability.
2Productivity
If the number of BF cores is increased to handle large polynomial degrees, then processing speed is improved, but the complexity of memory access and data management increases
Solution Approach 1:
The patent implements a universal memory access pattern where the same set of pipeline registers and memory access mechanisms serves all BF cores across different clock cycles. The dual-port data memory and shared register file provide multi-functional access for both read and write operations, eliminating the need for separate dedicated memory paths for each BF core.
Solution Approach 2:
The patent ensures continuous utilization of BF cores by pipelineing memory read and write operations across consecutive clock cycles. The dual-port memory allows overlapping read and write operations, and the pipeline registers maintain data flow continuity between cycles, ensuring that BF cores remain productive without idle waiting periods.
3Productivity
If dual-port data memory is used to enable simultaneous read and write operations, then throughput is improved, but the complexity of memory control and data routing increases
Solution Approach 1:
The patent implements dynamic control of the dual-port memory through a control unit that adapts memory access patterns based on the current clock cycle and active BF cores. The control unit dynamically routes data to appropriate registers and manages the read/write ports, allowing flexible memory access without requiring static complex routing infrastructure.
Data Source
AI summary
Systems and memory devices are disclosed for fully homomorphic encryption (FHE). The system may include a processing unit including: a data memory for storing coefficients for a polynomial; a twiddle factor (TF) memory for storing TF values associated with the polynomial; a TF register connected to the TF memory; a plurality of first registers connected to the data memory; a plurality of first MUXs connected to the first registers; a plurality of second registers connected to the plurality of first MUXs; a plurality of Butterfly (BF) cores connected to the plurality of the second registers and the TF register; wherein each of the plurality of BF cores is configured to, responsive to a control signal, perform a Butterfly Transform (BFT) operation based on two coefficients from the data memory and a TF value from the TF memory.