Fibre Channel and SCSI Frame Validation Circuits at Wire Speed

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Solution Overview

Problem

Software-based validation of data frames is time-consuming and not scalable, leading to bottlenecks and delays in data transfer as data flow increases, making it difficult to validate frames at wire speed.

Innovation Solution

Circuits are used to validate fibre channel and SCSI frames at wire speed by processing format and command information using gates, allowing for error information to be written in the frames and enabling scalable validation of data frames.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If software code is used to validate data frames, then validation can be performed with flexible logic and conditional branches, but processing time increases and wire speed validation cannot be achieved

Engineering Contradiction:

Improveframe validation accuracyVSAvoidframe processing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces software-based validation with hardware circuit implementation. The validation logic is transformed from software code with conditional branches into dedicated hardware circuits that perform validation operations in parallel, eliminating interpretation overhead and enabling wire-speed processing while maintaining validation accuracy

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The validation circuit is divided into multiple independent functional units that process different aspects of frame validation simultaneously. This segmentation allows parallel processing of validation tasks, increasing throughput while maintaining comprehensive validation coverage

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If software code is used to validate data frames, then validation logic can be implemented with conditional branches, but the system is not scalable when data flow increases

Engineering Contradiction:

Improvevalidation logic flexibilityVSAvoiddata throughput capacity

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The hardware validation circuit is designed with configurable parameters and adjustable operational characteristics. This allows the circuit to adapt to different data rates and frame types dynamically, providing both flexibility in validation logic and scalability in handling increased data flows without becoming a bottleneck

Inventive Principle:

Principle #15Dynamics

3Reliability

If software code with conditional branches is used for validation, then comprehensive validation can be performed, but bottlenecks occur when data flow increases

Engineering Contradiction:

Improvevalidation completenessVSAvoiddata transfer speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent substitutes software-based validation with hardware circuit implementation. The validation logic is transformed from software code with conditional branches into dedicated hardware circuits that perform validation operations in parallel, eliminating interpretation overhead and enabling wire-speed processing while maintaining validation accuracy

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The hardware validation circuit operates continuously without the intermittent execution characteristic of software. Validation occurs in every clock cycle without interruption for interpretation or context switching, ensuring both comprehensive validation and sustained high-speed data transfer capability

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS7596740B1Apparatus for processing fibre channel and SCSI frames at wire speed

Publication Date: 2009.09.29 NETAPP INC

AI summary

One or more circuits that validate data frames are provided. The validation may validate information for a fiber channel header and information for a small computer system interface (SCSI) header. The validation is performed by one or more circuits at wire speed.