FICON Check Word Caching for Faster CRC Seed Updates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing I/O processing systems incur inefficiencies due to the need for frequent memory read/write accesses to maintain the CRC seed after every 256-byte data transaction, leading to slow data flow and processing penalties.
Innovation Solution
Incorporating a timer and a CRC cache within the data router to reduce memory access penalties by periodically updating the CRC seed, allowing for faster data check word computation and processing of commands belonging to the same ACW.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the CRC seed is updated after every 256-byte chunk in memory, then the CRC check accuracy is maintained, but the memory access penalty increases and processing speed decreases
Solution Approach 1:
The patent pre-calculates and stores CRC seed values in a lookup table before processing begins. This preliminary action allows the system to retrieve pre-computed seed values during data processing without performing time-consuming memory updates after every 256-byte chunk, thus maintaining CRC accuracy while improving processing speed
Solution Approach 2:
The patent creates a copy of the CRC seed values in a dedicated lookup table structure within the I/O subsystem. This separate copy allows fast retrieval and processing without repeatedly accessing and updating the main memory, reducing memory access penalties while preserving the integrity of the original data and CRC calculations
2Reliability
If memory access is performed after every transaction to update CRC seed, then data integrity is verified, but memory access penalty increases leading to slower data transfer
Solution Approach 1:
The system performs preliminary CRC seed computation and stores results in a lookup table before actual data transfer begins. This eliminates the need for time-critical memory access during data transfer operations, maintaining data integrity verification while minimizing time loss
Solution Approach 2:
The patent introduces a lookup table as an intermediary structure between the CRC calculation logic and main memory. This intermediary allows the system to verify data integrity through pre-computed values without directly accessing slow main memory during critical data transfer operations, thus reducing memory access time while preserving reliability
3Device complexity
If CRC computation is performed without caching, then implementation simplicity is maintained, but I/O processing efficiency decreases due to repeated memory access
Solution Approach 1:
The patent implements a lookup table that copies and stores pre-computed CRC seed values in a readily accessible format within the I/O subsystem. This copying approach maintains implementation simplicity while dramatically improving I/O processing efficiency by eliminating repeated memory access operations
Solution Approach 2:
The system changes the organizational parameter of CRC data from scattered memory locations to a structured lookup table format. This parameter change optimizes data access patterns, allowing efficient CRC computation during I/O operations while keeping the implementation relatively simple through the use of standard table-lookup techniques
Data Source
AI summary
Technical solutions are described for computing data check word for a host request for an I/O processing operation at a host computer system that communicates with a control unit. An example method includes obtaining information for a first I/O operation at a channel subsystem in the host computer system, and accessing an address control word (ACW) of the first I/O operation. The ACW is stored in the local channel memory, and the ACW includes a first data check seed-value. The method also includes computing a first data check word based on the first data check seed-value from the ACW. The method also includes obtaining information for a second I/O operation at the channel subsystem, and in response to the second i/o operation corresponding to said ACW of the first I/O operation, computing a second data check word based on a second data check seed-value from a cache memory.